[Answered] Physical block size and physical page size of SPI flash for SPIFFs

[kolban]

I am studying SPIFFs as found here ... https://github.com/pellepl/spiffs/wiki/Configure-spiffs

The first question asked is to determine the physical block size and the physical page size of SPI flash storage. How would we determine these values for the common modules we use? For example, for the ESP-DevKitC where might those values be found?

[WiFive]

In the datasheet for the flash chip

[kolban]

That makes sense ... so I'm guessing that the general answer to the question is:

"SPI flash memory devices vary by manufacturers model. The best answer is to find the data sheet for the corresponding flash memory device that is actually the one in use. If you have a physical module, grab a magnifying glass and take a look at the board. If the flash memory chip is not visible (perhaps because it is covered in a shield and you don't want to remove the shield) then try and contact the supplier of the module and see if they can tell you the specs of the flash memory being used. Ideally, if one finds out, post that answer in a forum or newsgroup so that others may find that information in the future. Until one of us actually takes a look at the DevKitC board we don't yet the actual SPI flash memory device employed by Espressif".

[ESP_Sprite]

In general, though, I'd say that a rough estimate of 99.8% of all chips the ESP32 can interface with use the same block/page sizes (256byte page size, 4KiB erase block size)

[ESP_Angus]

Ideally, if one finds out, post that answer in a forum or newsgroup so that others may find that information in the future. Until one of us actually takes a look at the DevKitC board we don't yet the actual SPI flash memory device employed by Espressif".

The model details of flash chips used (for far) in WROOM32 can be found here:
http://www.esp32.com/viewtopic.php?t=386#p1776

Note that we don't guarantee future modules will use the exact same flash models, but they will be similar.

The summary Sprite gave is good to go on, and probably going to be true in all cases.

An addition piece of inof, the ESP32 SPI flash controller hardware can also issue 32KB Block Erase commands (For 32KB aligned regions). These are faster on most chips than erasing 8x4KB sectors individually.

EDIT: This post said 64KB for a while, but it's 32KB - at least for most flash chips.