A way to improve ADC signal to noise ratio (an idea)

[SergioUno]

I have been playing for a while with ESP32 ADCs, and clearly they are suffering from internal cross talk from other digital circuits. The ADC itself have decent linearity, but the noise is way above expectations.
The common way to deal with this is to shut down as much periphery as you can, so probably managing conversion from ULP while main CPUs is off will help in future. But meanwhile, what can we shut down to minimize noise to ADC and confirm the hypothesis? Does anyone already tried it? Theoretically even reducing CPU clock rate should help. What do you think?

[WiFive]

https://github.com/espressif/esp-idf/co ... cc2b96f913

[SergioUno]

Could you elaborate?

It looks like the thread you posted is intended to lower power consumption at the expense of increase noise of ADC:
+ ADC power can be controlled by the FSM instead of software. This allows the ADC to
+ be shut off when it is not working leading to lower power consumption. However
+ using the FSM control ADC power will increase the noise of ADC.

[WiFive]

Default before this recent change was
+ using the FSM control ADC power will increase the noise of ADC.

Also wrover-kit pcb layout has shown good noise performance

Just so you are aware of these factors