ESP WROVER Flash Size

[markwj]

Similar to the topic for WROOM-32, but for WROVER.

We can add an external 1.8v flash, external 1.8v regulator (as VDD_SDIO is not exposed), but the issue is the CS line for external flash.

Given that GPIO16 and GPIO17 (the last two remaining GPIOs in VDD_SDIO domain) are used for PSRAM inside the module, we have to use a 3.3v domain CS line. So, we use GPIO22 (as with our previous work on WROOM-32) but need to level shift down to 1.8v (as flash chip is not 3.3v tolerant). We chose a SN74LV1T34 level converter for that CS line (3.3v->1.8v).

Here are the eFuse settings we use:

Code: Select all

XPD_SDIO_FORCE         Ignore MTDI pin (GPIO12) for VDD_SDIO on reset    = 1 R/W (0x1)
XPD_SDIO_REG           If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset   = 1 R/W (0x1)
XPD_SDIO_TIEH          If XPD_SDIO_FORCE & XPD_SDIO_REG, 1=3.3V 0=1.8V   = 0 R/W (0x0)
SPI_PAD_CONFIG_CLK     Override SD_CLK pad (GPIO6/SPICLK)                = 6 R/W (0x6)
SPI_PAD_CONFIG_Q       Override SD_DATA_0 pad (GPIO7/SPIQ)               = 7 R/W (0x7)
SPI_PAD_CONFIG_D       Override SD_DATA_1 pad (GPIO8/SPID)               = 8 R/W (0x8)
SPI_PAD_CONFIG_HD      Override SD_DATA_2 pad (GPIO9/SPIHD)              = 9 R/W (0x9)
SPI_PAD_CONFIG_CS0     Override SD_CMD pad (GPIO11/SPICS0)               = 22 R/W (0x16)
DISABLE_SDIO_HOST      Disable SDIO host                                 = 0 R/W (0x0)

Concerned about the speed of the level shifter. Spec sheet indicates 5ns or so propagation delay, so success will depend on the delay time in the ESP32 when switching CS between PSRAM and flash.

Booting with PSRAM disabled works just fine. But, as we suspected, with PSRAM enabled we get a crash accessing the PSRAM:

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rst:0x1 (POWERON_RESET),boot:0x3f (SPI_FAST_FLASH_BOOT)
configsip: 156795334, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0018,len:4
load:0x3fff001c,len:4468
load:0x40078000,len:0
load:0x40078000,len:12988
entry 0x40078d14
Guru Meditation Error: Core  0 panic'ed (LoadProhibited)
. Exception was unhandled.
Register dump:
PC      : 0x401370c8  PS      : 0x00060530  A0      : 0x400da3ac  A1      : 0x3ffe3b90
0x401370c8: mg_if_recv_tcp_cb at .../components/mongoose/src/mongoose.c:11367

0x400da3ac: psram_read_id at ../esp-idf/components/esp32/./spiram_psram.c:331

A2      : 0x3ffe3bd0  A3      : 0x000000e1  A4      : 0x0ffd114c  A5      : 0x00000000
A6      : 0x000008ff  A7      : 0x00000001  A8      : 0x00001b00  A9      : 0x00001000
A10     : 0x00000b00  A11     : 0x0ffd104f  A12     : 0x00000034  A13     : 0x00000000
A14     : 0x000008ff  A15     : 0x00000004  SAR     : 0x00000017  EXCCAUSE: 0x0000001c
EXCVADDR: 0x00001024  LBEG    : 0x4009b028  LEND    : 0x4009b033  LCOUNT  : 0x00000000
0x4009b028: memset at /home/jeroen/esp8266/esp32/newlib_xtensa-2.2.0-bin/newlib_xtensa-2.2.0/xtensa-esp32-elf/newlib/libc/machine/xtensa/../../../../.././newlib/libc/machine/xtensa/memset.S:142

0x4009b033: memset at /home/jeroen/esp8266/esp32/newlib_xtensa-2.2.0-bin/newlib_xtensa-2.2.0/xtensa-esp32-elf/newlib/libc/machine/xtensa/../../../../.././newlib/libc/machine/xtensa/memset.S:152

Backtrace: 0x401370c8:0x3ffe3b90 0x400da3a9:0x3ffe3bd0 0x400d7d39:0x3ffe3c00 0x4008156a:0x3ffe3c20 0x40078aa6:0x3ffe3c40 0x40078b59:0x3ffe3c70 0x40078ced:0x3ffe3cb0 0x40078e36:0x3ffe3e70 0x40007c31:0x3ffe3eb0 0x4000073d:0x3ffe3f20
0x401370c8: mg_if_recv_tcp_cb at ../components/mongoose/src/mongoose.c:11367

0x400da3a9: psram_read_id at ../esp-idf/components/esp32/./spiram_psram.c:330

0x400d7d39: esp_spiram_init at ../components/esp32/./spiram.c:109

0x4008156a: call_start_cpu0 at ../components/esp32/./cpu_start.c:149

It seems to have started to run app code, but then crashed out switching back to PSRAM.

Any ideas? Fastest level converter I can find is still around 1.x ns.

[markwj]

P.S. Reading the source code, it seems that PSRAM CLK is also delayed wrt SPI CLK, which could mess things up further:

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esp-idf/components/esp32/./spiram_psram.c
esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode)   //psram init
...
/* We need to delay CLK to the PSRAM with respect to the clock signal as output by the SPI peripheral.
We do this by routing it signal to signal 224/225, which are used as a loopback; the extra run through
the GPIO matrix causes the delay. We use GPIO20 (which is not in any package but has pad logic in
silicon) as a temporary pad for this. So the signal path is:
SPI CLK --> GPIO28 --> signal224(in then out) --> internal GPIO29 --> signal225(in then out) --> GPIO17(PSRAM CLK)
*/

[loboris]

Not related to the issue, but I just don't understand why ESP32-WROVER is not available in 8/16 MB Flash version. The price impact should be minimal.

[markwj]

Not related to the issue, but I just don't understand why ESP32-WROVER is not available in 8/16 MB Flash version. The price impact should be minimal.

Kind of related; I too can't understand why they don't make the option available. Without VDD_SDIO exposed, and without any 1.8v domain GPIOs available, this is truly a PITA.

Although given the price difference 4MB vs 8MB vs 16MB, I'd forget about the 8MB.

MOQ for custom 16MB version is 6,000 units (or at least was for WROOM-32).

[markwj]

A review of the code brings up these gems:

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/components/esp32/spiram_psram.c
// IO-pins for PSRAM. These need to be in the VDD_SIO power domain because all chips we
// currently support are 1.8V parts.
// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
// hardcode the flash pins as well, making this code incompatible with either a setup
// that has the flash on non-standard pins or ESP32s with built-in flash.
#define FLASH_CLK_IO      6  //Psram clock is a delayed version of this in 40MHz mode
#define FLASH_CS_IO       11
#define PSRAM_CLK_IO      17
#define PSRAM_CS_IO       16
#define PSRAM_SPIQ_IO     7
#define PSRAM_SPID_IO     8
#define PSRAM_SPIWP_IO    10
#define PSRAM_SPIHD_IO    9

So GPIO11 is hard coded as flash CS.

Code: Select all

/* We need to delay CLK to the PSRAM with respect to the clock signal as output by the SPI peripheral.
We do this by routing it signal to signal 224/225, which are used as a loopback; the extra run through
the GPIO matrix causes the delay. We use GPIO20 (which is not in any package but has pad logic in
silicon) as a temporary pad for this. So the signal path is:
SPI CLK --> GPIO28 --> signal224(in then out) --> internal GPIO29 --> signal225(in then out) --> GPIO17(PSRAM CLK) */

Why?

[markwj]

By fixing FLASH_CS_IO in components/esp32/spiram_psram.c, I get further:

Code: Select all

I (685) boot: Loaded app from partition at offset 0x10000
I (686) boot: Disabling RNG early entropy source...
Guru Meditation Error: Core  0 panic'ed (LoadProhibited)
. Exception was unhandled.
Register dump:
PC      : 0x400da37f  PS      : 0x00060530  A0      : 0x800da3ac  A1      : 0x3ffe3b30
0x400da37f: psram_disable_qio_mode at /Users/mark/esp3o/esp-idf/components/esp32/./spiram_psram.c:317

A2      : 0x00000001  A3      : 0x00000000  A4      : 0x00000034  A5      : 0x00000000
A6      : 0x000008ff  A7      : 0x00000004  A8      : 0x00000000  A9      : 0x3ff4413c
A10     : 0x00000000  A11     : 0x00000000  A12     : 0x00000018  A13     : 0x00000000
A14     : 0x00000000  A15     : 0x00000001  SAR     : 0x00000017  EXCCAUSE: 0x0000001c
EXCVADDR: 0x800da3ac  LBEG    : 0x4009b028  LEND    : 0x4009b033  LCOUNT  : 0x00000000
0x4009b028: memset at /home/jeroen/esp8266/esp32/newlib_xtensa-2.2.0-bin/newlib_xtensa-2.2.0/xtensa-esp32-elf/newlib/libc/machine/xtensa/../../../../.././newlib/libc/machine/xtensa/memset.S:142

0x4009b033: memset at /home/jeroen/esp8266/esp32/newlib_xtensa-2.2.0-bin/newlib_xtensa-2.2.0/xtensa-esp32-elf/newlib/libc/machine/xtensa/../../../../.././newlib/libc/machine/xtensa/memset.S:152

Backtrace: 0x400da37f:0x3ffe3b30 0x400da3a9:0x3ffe3b80 0x40084299:0x3ffe3bd0 0x400d7d39:0x3ffe3c00 0x4008156a:0x3ffe3c20 0x40078c6a:0x3ffe3c40 0x40078d1d:0x3ffe3c70 0x40078f8e:0x3ffe3cb0 0x400790d6:0x3ffe3e70 0x40007c31:0x3ffe3eb0 0x4000073d:0x3ffe3f20
0x400da37f: psram_disable_qio_mode at /Users/mark/esp3o/esp-idf/components/esp32/./spiram_psram.c:317

0x400da3a9: psram_read_id at /Users/mark/esp3o/esp-idf/components/esp32/./spiram_psram.c:330

0x40084299: psram_enable at /Users/mark/esp3o/esp-idf/components/esp32/./spiram_psram.c:558 (discriminator 6)

0x400d7d39: esp_spiram_init at /Users/mark/esp3o/esp-idf/components/esp32/./spiram.c:109

0x4008156a: call_start_cpu0 at /Users/mark/esp3o/esp-idf/components/esp32/./cpu_start.c:149

But note my flash is in DIO mode (as QIO doesn't work for external flash).

[markwj]

Note: Raised the hard-coded GPIOs issue as a bug:

https://github.com/espressif/esp-idf/issues/1563