ESP32 as a SWD debugger (and maybe JTAG)

[PaulFreund]

I would like to use the ESP32 as a debugger to read and write memory/registers and maybe debug other connected processors.

I see different ways of achieving this, depending on what the peripherals of the ESP32 allow and here I would like to have your feedback.

• SWD has its similarities to SPI (see https://www.arm.com/files/pdf/Serial_Wire_Debug.pdf page 6) and to me it looks like I can use an SPI master to talk SWD effectively, using only command, read and write phase (see https://esp-idf.readthedocs.io/en/v2.0/ ... aster.html)
  
  If the SPI master is not suitable for this task, could it be possible to use CPU1 and bit bang the protocol using GPIO while CPU0 is handling network protocols? Or are there synchronisation issues with the GPIOs that will slow down CPU0 a lot or delay the GPIOs.
  
  Other options of course include searching for an external peripheral that does the fast processing and then connecting that using any of the ESP32's buses.
  
  Now second question, I have seen there are JTAG pins on the processor, is there a peripheral behind it that allows to act as JTAG master?

Thank you very much

[ESP_Angus]

Hi Paul,

(This is not official Espressif advice, but I've messed around with debug protocols a bit and I think this is a cool idea, so I can give you some tips.)

If possible, try to obtain a copy of the "ARM Debug Interface Architecture Specification" document. It used to be downloadable from ARM after registration, probably still is.

SWD may work via SPI, but remember there are some restrictions:

• The same data pin is used to read and write, so during the "bus turnaround" phases described in the datasheet you have to be able to swap the GPIO used for SWD between output and input.
• The host has to be able to respond to non-OK ACK responses from the target. You can get around this a bit by setting the "sticky" error bits in the target's debug control registers, so any FAULT/WAIT response will ignore the data phase (which is sent anyhow) and then the host can recover by clearing the "sticky" error.

If you want to treat SWD as pure SPI, you can probably use the so-called "SWD resistor hack" that openocd uses to drive SWD from JTAG debuggers. ie you use separate ESP32 pins for MISO and MOSI, but put a series resistor between MOSI and SWD so that the target can still drive the bus and the ESP32 can read it via MISO.

Regarding JTAG, the onboard JTAG port is unfortunately not helpful as a JTAG bus master. However JTAG is extremely similar to SPI, more similar than SWD, so you should be able to use the SPI master peripheral in some way.

Bit-banging both protocols via GPIOs is also an option. As the host generates the clock for both JTAG and SWD, I don't think you have to worry too much about precise timing.

Look forward to seeing how your project proceeds.

[PaulFreund]

Hi Angus,

thank you very much for your description! I will definitely update you with my progress

[PaulFreund]

I got it to work! Without hardware hacking The SPI master has a 3-Wire mode.

To add frosting to the cake it is implemented to a level that allows memory/flash reading and writing with ready made functions thanks to the work of libSWD!

Next topic for me is to investigate if I can use urJTAG and if it is possible/the right idea to port openocd to be able to use the ESP32 as a debugger, any thoughts on that? I haven't read into what openocd really is.

[PaulFreund]

PS: I will publish some code in the following days

[PaulFreund]

Sorry this took so long, here is the code as a component:

https://github.com/PaulFreund/libSWD-esp32

It should be able to use all features of libSWD, I only tired to read the ID code and memory data by address so far. I tested successfully with up to 40Mhz and because of the handy 3-wire mode in the SPI master I didn't even have to use a hardware hack. Next thing is maybe JTAG.

[ESP_Angus]

Sorry this took so long, here is the code as a component:

https://github.com/PaulFreund/libSWD-esp32

It can read ID code as well as memory data by address. I tested successfully with up to 40Mhz and because of the handy 3-wire mode in the SPI master I didn't even have to use a hardware hack. Next thing is maybe JTAG.

Nice job! I had actually missed that we have SPI_DEVICE_3WIRE mode, that is very handy.

[rudi ;-)]

Sorry this took so long, here is the code as a component:

https://github.com/PaulFreund/libSWD-esp32

It can read ID code as well as memory data by address. I tested successfully with up to 40Mhz and because of the handy 3-wire mode in the SPI master I didn't even have to use a hardware hack. Next thing is maybe JTAG.

Nice job! I had actually missed that we have SPI_DEVICE_3WIRE mode, that is very handy.

+1