What would you like to see in The Next Chip?
Re: What would you like to see in The Next Chip?
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ESP_Sprite
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Re: What would you like to see in The Next Chip?
I warned you in a PM that we do not accept offtopic ranting here: please keep to technical details. You have made your opinions about the direction you think Espressif is going in and your hopes/wishes/predictions re. our CEO loud and clear, no need to repeat them in every single post you make.
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ESP_krzychb
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Re: What would you like to see in The Next Chip?
Indeed. Open a separate topic to discuss it.Leitukey wrote: The "elephant in the room" is the following question. Is Espressif going build products that are generally suitable merely for toys, trinkets, and the like or is Espressif going to build products suitable for significant consumer and industrial products? This is not something that can be properly decided merely by bandying around arcane technical arguments but rather it requires a proper understanding of many different facets of Espressif particularly and of technology companies generally.
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ESP_Sprite
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Re: What would you like to see in The Next Chip?
Leitukey: Again: your point is clear but offtopic and does not bear repetition in a location where we want a technical discussion to take place: I removed its contents.
Re: What would you like to see in The Next Chip?
A new very fast interface to inter connect esp32s together, this will increase almost everything compared with a single esp32.
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ESP_Sprite
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Re: What would you like to see in The Next Chip?
Agree007: That is an interesting idea. Do you have any thoughts on how this would work in practice?
Re: What would you like to see in The Next Chip?
It should be a combination of hardware, dedicated logic and pins, and software/api library.
Im have been working on a solution using standard pins, but I need to test it more to verify functionality, speed etc.
If you build/implement it right in hw/sw you will be able to interconnect a number of asics, to increase number of wifi, ic2, spi, user memory?
Just my 2 cents I'm not a asic guide
Im have been working on a solution using standard pins, but I need to test it more to verify functionality, speed etc.
If you build/implement it right in hw/sw you will be able to interconnect a number of asics, to increase number of wifi, ic2, spi, user memory?
Just my 2 cents I'm not a asic guide
Re: What would you like to see in The Next Chip?
This has probably been said, but IIRC, the current board has a standard FPU. If at all possible I'd like to see the next iteration be capable of double precision operations in the same time as floating point operations. I don't have a good enough understanding of the xtensia architecture in order to say that this is not already true.
Also, as far as cutting goes, most BLE blutooth modules today are 10$. the Wifi capabilities are much more important, IMO.
If you plan on upping the clock rate, some L1 cache would be nice..
Also, as far as cutting goes, most BLE blutooth modules today are 10$. the Wifi capabilities are much more important, IMO.
If you plan on upping the clock rate, some L1 cache would be nice..
Re: What would you like to see in The Next Chip?
Hardware & software protections against (mainly during the secure boot computations/checks...):
Of course those protections should be validated by some independent organism to certify MCU is protected against those types of attacks
- Clock Glitch Attacks
- Power Glitch Attacks
- SCA (Side Channel Attacks)
- FA (Fault Attacks)
- DFA (Differential Fault Analysis)
Of course those protections should be validated by some independent organism to certify MCU is protected against those types of attacks