C6 Validation for schematic + selection of Flash NOR Chip

[fasani]

Hello Hardware forum,
I've committed last week a bad mistake and selected a C6 QFN40 for a design forgetting that this version does not come with built in flash.
So in order to avoid changing it for the more expensive QFN32 (With 4 MB Flash) I decided to go a step forward and add for the first time a QSPI flash chip in my design. I've read in this post: https://esp32.com/viewtopic.php?f=12&t= ... ip#p137020 about a model called W25Q128.
Is there any list of LCSC components that can be used and are already tested to work?

I would like to test this model: AT25DF321A-SH-T https://jlcpcb.com/partdetail/6955-AT25DF321A_SHT/C6490

Attaching the relevant part of the schematics.
Full Schematics in PDF: https://github.com/martinberlin/H-C6-ulp/

This is open source design if anyone wants to suggest something or be part of the project please let us know.
We are designing a low power PCB that will bit-bang SPI using ULP low power processor (SPI is of course slower but you can move a display consuming 1.5 mA per hour)

About consumption of this flash chip I see that in a typical Read operation will consume from 15 to 19 mA and is fed by a GPIO (SPI_VDD) is that OK? Or should I also optionally add a 3V3 power source?