esp32 pid controller and cache/mmu for external memory

[yamamoto]

hi,

i'm experimenting to use pid controller to switch mmu mappings for external memory.
(my current focus is spiram, not flash)

i have a few questions.

* is this a viable approach at all? (known erratas etc?)
* is the cache tagged with virtual address? (vivt?)
* when using pid controller, does the cache tag contain pid as well?

[yamamoto]

i noticed that, when using psram, nuttx uses pid 1 instead of pid 5.
https://github.com/apache/nuttx/blob/82 ... .h#L64-L65
does it imply that pid 0/1 have something special wrt cache/mmu?

[MicroController]

ESP32 TRM:

The MMU mapping configuration registers [...] are only accessible from processes with a PID of 0 or 1;

because

processes with PID of 0 or 1 are elevated processes with higher authority compared to processes with PID
ranging from 2 ~ 7.

[yamamoto]

thank you for the comment. but i don't think it explains.
in case of nuttx, pid 1 vs 5 is about userspace. the control registers are accessed by the kernel, which is always pid 0.

[MicroController]

I think in that case you'd have to check with the NuttX developers on why they need a dedicated PID for external memory allocation in the first place when the kernel running at PID 0 could just do it directly.
My assumption is that these allocations/MMU register accesses are actually not done by the PID 0 kernel itself.

[yamamoto]

i found a possible cause since then.
https://github.com/apache/nuttx/issues/13761
i guess the use of pid 1 was a workaround for this problem.