I2C failures when ESP is busy

[achugbgl2]

Hi all

I'm seeing some weird issues with I2C transmissions. Normally, everything works fine but sometimes, I'll see this behavior where there is a random 45ms delay mid-transmission which then results in a failure. See example below:

I2C failure example.png (31.87 KiB) Viewed 1133 times

I've seen this happen with both reads and writes and with multiple chips on our board. It seems to happen when the ESP is busy. For us, it happens during an OTA update when writing incoming data to a temporary SPIFFS partition.

Any ideas as to why this could be happening?

Thanks!

[MicroController]

45ms delay mid-transmission which then results in a failure.

What "failure" do you see? Where?
Is the ESP the I2C master or a slave?

it happens [...] when writing [...] to a temporary SPIFFS partition.

This is not unexpected. Note that a) writes to flash can take a 'long' time, especially with SPIFFS, and b) during every write to the flash, most things in the ESP are halted; specifically, all tasks except for the one performing the write and all ISRs which are not placed in and registered as IRAM.

[achugbgl2]

The ESP is the I2C master. It seems like the delay causes the slave chips to not ACK the transmission which then errors out the ACK checks on the ESP side?

This is not unexpected. Note that a) writes to flash can take a 'long' time, especially with SPIFFS, and b) during every write to the flash, most things in the ESP are halted; specifically, all tasks except for the one performing the write and all ISRs which are not placed in and registered as IRAM.

I see. Is it normal for the file writing to halt the rest of the chip even in the middle of a single I2C transmission?

[MicroController]

The ESP is the I2C master. It seems like the delay causes the slave chips to not ACK the transmission which then errors out the ACK checks on the ESP side?

This could be. Some slaves may not allow extended pauses within one transaction.

Is it normal for the file writing to halt the rest of the chip even in the middle of a single I2C transmission?

Not quite sure about that. From a quick look at the (legacy) I2C driver's code, it seems like a single transaction, once handed over to the driver, should be able to be processed by driver code in IRAM.
Which IDF version and I2C driver are you using?
With the "legacy" driver ("i2c.h"), you can try passing ESP_INTR_FLAG_IRAM to i2c_driver_install(...) to enable I2C interrupt handling during flash writes.

[achugbgl2]

Gotcha. Looks like I'm on IDF 5.1.1 and using the legacy driver. I will try the ESP_INTR_FLAG_IRAM as well as see if the problem persists with the newer I2C driver. Thank you!