SPI as only input pins in slave mode

[Singe12]

Hi,

I see that I've 6 pins that are only input, from pin 5 to pin 11. Since I need to set an SPI Peripheral as Slave on ESP32 device, I want to ask if Clock, MOSI and CS can be placed on this Input only pins since I don't need that ESP32 drive them. Also, if I choose this pins as SPI, I still have 80Mhz as speed and DMA?

p.s. anyone have sperimented SPI max. limits as slave?

Thank you!

[hydrabus]

You question is very interesting as I have same type of use case in mind.

I think for this use case it is mandatory to use SPI DMA with FIFO (as there is FIFO in SPI with DMA see esp-idf/components/esp32/include/soc/spi_reg.h => SPI_OUT_EOF_MODE)
In order to do some treatment in asynchronous manner on data received especially at 80mbit/s (especially to do not loose data if SPI internal FIFO is too short and the CPU has not read the data in time ...)

Idea:
Use SPI DMA controller to write data(producer) in shared RAM though (SPI_AHBM_FIFO ?) and in parallel CPU read data(consumer) and do treatment on them ...

Maybe there is also a HW FIFO (configurable in size and addr start) in ESP32 which can be linked to SPI DMA (or other devices) to easily permit to push data from DMA controller to this FIFO and then CPU can read data from it in transparent way without any software overhead ... (like when we use a software FIFO which requires managing consumer/producer index (or even circular buffer to read/write multibyte), full/empty flag and even cache coherency ...)

Anyway there is lot of missing information about that now ...

Waiting for Espressif to have more details on this use case and what is possible to do with ESP32

[ESP_Sprite]

The HW fifo is pretty small; I think it consists of the W registers only for a total of 16*4=64 bytes. In DMA mode, it is used as a transparent buffer to stop DMA slowdowns from interrupting the SPI stream, as well as allowing DMA bursts. From a programmers view, it is entirely transparent, as in you don't have to worry about it, it will essentialy be like your DMA transfer is immediately consumed by the SPI peripheral.

Yes, you can use the input-only pins as SPI input pins. You'll need to run them through the GPIO matrix for that, though, which incurs a 2 clock cycle (of the 80MHz APB clock) latency and limits the max clock frequency to 40MHz.

[Singe12]

The HW fifo is pretty small; I think it consists of the W registers only for a total of 16*4=64 bytes. In DMA mode, it is used as a transparent buffer to stop DMA slowdowns from interrupting the SPI stream, as well as allowing DMA bursts. From a programmers view, it is entirely transparent, as in you don't have to worry about it, it will essentialy be like your DMA transfer is immediately consumed by the SPI peripheral.

Yes, you can use the input-only pins as SPI input pins. You'll need to run them through the GPIO matrix for that, though, which incurs a 2 clock cycle (of the 80MHz APB clock) latency and limits the max clock frequency to 40MHz.

Ok, so every pins that are not from 17 to 39 pin (pins with SPI function) are slowed cause GPIO matrix and the only pins to reach 80Mhz in input and output are this dedicated pins?

[ESP_Sprite]

Yes, it comes down to that, more or less. If you need 80MHz, you have some freedom in mapping the peripherals; see page 4 (table IO_MUX) of http://www.espressif.com/sites/default/ ... ist_en.pdf . If you can't make it work with these pins, you can route them through the GPIO matrix, but this will limit the speed.

Some more details: The 40MHz limitation only is for input signals; signals going from the chip to the outside world can actually be 80MHz. Also, the SPI peripherals have a register to compensate for the added 2 cycles latency.

[sgctronic]

Hi,
in the reference manual (chapter 5.4) it is stated that the maximum input clock frequency of the ESP32 GP-SPI slave is fapb/8.
Does it mean that in SPI slave mode the maximum communicatino frequency is 10 MHz?

Best regards.

[ESP_Sprite]

If I recall correctly, the thing is that all signals, including the clock signal, are latched at the 80MHz APB bus. This means that you can have a theoretical maximum of 40MHz SPI clock, but that is only if you have a duty cycle that is exactly 50%. I think the hardware engineers stated a lower maximum frequency in order to make sure even 'weird' duty cycles lead to good results.

[trancefreak]

I also have this setup that I use the ESP32 as SPI slave. I have MOSI, CS on input only pins and this works. I also want to have CLK on an input only pin for the slave setup to free up as many output pins as possible but configuring CLK on an input only pin brings up an error message that this is not supported.

Can someone confirm that this should be possible or is having CLK on an input only pin not supported?

In previous posts I have read that it is necessary to do some pin muxing when having such a setup. Does the SPI slave driver handle this for me or do I have to do it manually?

Kind Regards,
Christian

[trancefreak]

Please, can someone from Espressif give an update on the issue with CLK routed to an input pin?

[ESP_Sprite]

Sounds like a bug. Can you create an issue for this on our Github repo, so we can track this?