[Q] DIO/QIO Spi Mode - what is the reason for different using in Soc's

[rudi ;-)]

hi
i wonder me, why in some hw configs QIO mode is used and in other only DIO.
what is the reason for using IO16, IO17 ( GPIO ) in D2WD, PICO-D4, if they are limited ( DIO )
why we use not 6,7,8,9,10,11 ( QIO ) in each SoC?

i know this state is not 100 prozent right and is meaningless
but i wonder anyway

best wishes
rudi

edit: typo

[ESP_igrr]

I am not sure I understand your question, but I think you should be able to use QIO mode on D2WD and PICO. The SoCs are not limited to DIO.

Just did a test here — selected QIO mode in menuconfig, uploaded to a D2WD board, got this:

Code: Select all

I (51) boot: ESP-IDF v3.0-dev-388-g1c4ad533 2nd stage bootloader
I (51) boot: compile time 12:39:01
I (52) boot: Enabling RNG early entropy source...
D (106) qio_mode: Probing for QIO mode enable...
D (149) qio_mode: Raw SPI flash chip id 0x15709d
D (192) qio_mode: Manufacturer ID 0x9d chip ID 0x7015
I (239) qio_mode: Enabling QIO for flash chip ISSI
D (290) qio_mode: Initial flash chip status 0x2
D (339) qio_mode: Updated flash chip status 0x40
D (376) qio_mode: Enabling QIO mode...
D (411) bootloader_flash: mmu set block paddr=0x00000000 (was 0xffffffff)
D (474) boot: magic e9
D (496) boot: segments 04
D (521) boot: spi_mode 02
D (546) boot: spi_speed 00
D (572) boot: spi_size 01
I (597) boot: SPI Speed      : 40MHz
I (636) boot: SPI Mode       : QIO
I (674) boot: SPI Flash Size : 2MB

On the PICO (note that i got a part w/ 2MB flash here; production parts should be 4MB):

Code: Select all

I (52) boot: ESP-IDF v3.0-dev-388-g1c4ad533 2nd stage bootloader
I (52) boot: compile time 12:39:01
I (53) boot: Enabling RNG early entropy source...
D (107) qio_mode: Probing for QIO mode enable...
D (150) qio_mode: Raw SPI flash chip id 0x15709d
D (193) qio_mode: Manufacturer ID 0x9d chip ID 0x7015
I (241) qio_mode: Enabling QIO for flash chip ISSI
D (291) qio_mode: Initial flash chip status 0x2
D (340) qio_mode: Updated flash chip status 0x40
D (377) qio_mode: Enabling QIO mode...
D (412) bootloader_flash: mmu set block paddr=0x00000000 (was 0xffffffff)
D (475) boot: magic e9
D (498) boot: segments 04
D (523) boot: spi_mode 02
D (547) boot: spi_speed 00
D (573) boot: spi_size 01
I (598) boot: SPI Speed      : 40MHz
I (637) boot: SPI Mode       : QIO
I (675) boot: SPI Flash Size : 2MB

Regarding the reason for choosing different IOs: this has to do with the bonding process. Not being a specialist in that domain, i can't explain this very well, but basically the choice of pads is determined by the physical location of pads on the ESP32 die and on the flash die.

[rudi ;-)]

thank you ivan! this helped in PICO-D4 and yes - figured it out now, many thanks.

have not sayed, that i did this with "future/psram-malloc" branch
there is in bootloader support for D2WD but not PICO-D4

Code: Select all

static void enable_qio_mode(read_status_fn_t read_status_fn,
                            write_status_fn_t write_status_fn,
                            uint8_t status_qio_bit)
{
    uint32_t status;
    const uint32_t spiconfig = ets_efuse_get_spiconfig();

    if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) {
        // spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP.
        //
        // For now, in this situation we only support Quad I/O mode for ESP32-D2WD where WP pin is known.
        uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_RESERVE);
        ESP_LOGE(TAG, "Note: chip_ver = %d", chip_ver);
        uint32_t pkg_ver = chip_ver & 0x7;
        ESP_LOGE(TAG, "Note: pkg_ver = %d", pkg_ver);
        const uint32_t PKG_VER_ESP32_D2WD = 2; // TODO: use chip detection API once available
        if (pkg_ver != PKG_VER_ESP32_D2WD) {
	    // ESP_LOGE(TAG, "Quad I/O is only supported for standard pin numbers or ESP32-D2WD. Falling back to Dual I/O.");
	    ESP_LOGE(TAG, "Quad I/O is only supported for standard pin numbers but will try on Pico-D4 it ;-)");
        /* for a test with PICO-D4 */
		// return;
        }
    }

    esp_rom_spiflash_wait_idle(&g_rom_flashchip);

    status = read_status_fn();
    ESP_LOGD(TAG, "Initial flash chip status 0x%x", status);

    if ((status & (1<<status_qio_bit)) == 0) {
        execute_flash_command(CMD_WREN, 0, 0, 0);
        write_status_fn(status | (1<<status_qio_bit));

        esp_rom_spiflash_wait_idle(&g_rom_flashchip);

        status = read_status_fn();
        ESP_LOGD(TAG, "Updated flash chip status 0x%x", status);
        if ((status & (1<<status_qio_bit)) == 0) {
            ESP_LOGE(TAG, "Failed to set QIE bit, not enabling QIO mode");
            return;
        }

    } else {
        ESP_LOGD(TAG, "QIO mode already enabled in flash");
    }

    ESP_LOGD(TAG, "Enabling QIO mode...");

    esp_rom_spiflash_read_mode_t mode;
#if CONFIG_FLASHMODE_QOUT
    mode = ESP_ROM_SPIFLASH_QOUT_MODE;
#else
    mode = ESP_ROM_SPIFLASH_QIO_MODE;
#endif

    esp_rom_spiflash_config_readmode(mode);

    esp_rom_spiflash_select_qio_pins(ESP32_D2WD_WP_GPIO, spiconfig);
}

qio-test.png (36.82 KiB) Viewed 10667 times

for this fast test i comment out simply the "return", will add pkg_ver later,
cause must be 5 usually



btw:
hope the bonding has "High Speed SPI character" cause can disturb the lines on psram later

txs again!


best wishes
rudi