ESP32-C5: maximum number of I2S slots ?

[harald.milz]

For my project which involves streaming 8 audio channels at 24 bit / 44.1 kHz between two devices I envision using ESP32's over WiFi (UDP or ESP-NOW to thwart latency). Alas, the ESP-IDF documentation says for ESP32-S3 and C6 that

"... due to the hardware limitation, only up to 4 slots are supported while the slot is set to 32 bit-width, and 8 slots for 16 bit-width, 16 slots for 8 bit-width. ... "

The Technical Reference Manual for the C6 adds 24 bit / 5 slots to the list above.

Am I right to assume this HW limitation is a 128 bit TX/RX buffer?

The H2 and the P4 explicitly have no such limitation but obviously these chips will not be suitable for my project (too slow / no WiFi). Looking at the ESP-IDF code in github, it appears that the definition for I2S_TX_TDM_WS_WIDTH is equal to 0x7f (127) for the devices with the limitation (S3, C3, C6) and 0x1ff (511) for P4 and H2. For C5 and C61, this value is also 0x1ff. Does this imply (may I expect) the C5 in particular not having said limitation, i.e. will I be able to run an 8-channel ADC / DAC at 24 bits with this chip in TDM256 mode? Or, alternatively, will it have 2 I2S controllers like the S3?

(N.B. The workaround of using an S3 with 2 4-slot ADCs and DACs is not feasible for me because the setup is supposed to be used in "noisy" WiFi environments, for which 802.11n is not really suitable, but WiFi6 is, in particular in the 5 GHz band which is much less congested. Hence my hope for the C5.)

TIA!