simultaneous setting of GPIO outputs for H-bridge control, how to?

[RalphD]

Hi there I am trying to implement a simple stepper motor driver using two H-bridges using ESP IDF. The requirement is that the GPIO's (4 of them) are set simultaneously. My firmware programmer seem to not be able to achieve this.

I understand that this requires setting the GPIO's by writing directly to the register for the logic level output of the GPIO's very likely as a full word including all other required GPIO output level affected by the register.

Am I right?

Thanks for any insight for a hardware engineer

[MicroController]

Hi there I am trying to implement a simple stepper motor driver using two H-bridges using ESP IDF. The requirement is that the GPIO's (4 of them) are set simultaneously.

Have you considered that you may actually want to have a dead-time in the switching?
Also, given that the motor is a mechanical system, and has comparatively huge inductances, a microsecond or so of delay between switching of the transistors will probably not make any difference. Just make sure you switch OFF the respective transistors in a bridge before switching ON the other ones.

I understand that this requires setting the GPIO's by writing directly to the register for the logic level output of the GPIO's very likely as a full word including all other required GPIO output level affected by the register.

Am I right?

Yes, modifying the corresponding bits in the 32-bit IO register would get it done, i.e. the usual REG = (REG & ~MASK) | (bitsToSet & MASK).
However, this makes the register update non-atomic, which may interfere with concurrent IO from other tasks/ISRs. And if you need to use IO pins from above and below GPIO31 at the same time, you'll need two 32-bit register accesses anyway, making the output non-simultaneous.

If you can accept a tiny delay (sub-microsecond) between clearing and setting of bits, you should look into using the W1TC and W1TS registers which enable you to atomically clear or set, respectively, any number of bits in a GPIO register via a single write.

[RalphD]

that is exactly the hint I was looking for, thanks

[djixon]

You didn't specified exact ESP chip you are using. Some of them (i.e. ESP32S3) are "equiped" with dedicated GPIO module cappable to simultaneously write up to 8 GPIOs (doesn't matter if some are above GPIO31 boundary and some are within GPIO0-31) within the same clock cycle.

You also didn't specify design for your motor driver, however, if it uses full H-bridge with separated control signals for N-channel and P-channel MOSFETS then you DO NOT WANT, UNDER ANY CIRCUMSTANCES those separted control lines are written in different cycles (doesn't matter how small time difference is), because for that time you will have direct short-circuit (through N-MOS and P-MOS pair) in between your power-line and GND!!!
In such a situation its much better to use an external, fast enough, transistor to invert (lets say N-channel gate signal) and provide (lets say inverted P-channel gate signal). That way you only need one signal per half of full H bridge. So in total there will be only 2 signals for full H-bridge (because of two transistors involved) instead of 4 signals a raw H bridge contains.

[MicroController]

you DO NOT WANT, UNDER ANY CIRCUMSTANCES those separted control lines are written in different cycles

Except when you do want the dead time, specifically to avoid the transient 'short circuit' you get when switching the P's and N's simultaneously.

[djixon]

@MicroController You are tlaking about "diagonal" mosfets in standard full H bridge with 4 gates. They controll current through load. Now tell me what is going to happen if you on already oppened N-MOSFET at "left" side of load, you open P-MOSFET at the same "left" side of load during writtes not within the same cycle (so write for closing N-MOS is delayed because it didn't happen within the same cycle together with write for gate of P-MOSFET)?

Direct short circuit from power line to ground at that "left" side through both left pair of MOSFETs !!!!

[mikemoy]

RalphD, did you know there is already an example for this in the examples folder ?

[MicroController]

You are tlaking about "diagonal" mosfets in standard H bridge with 4 gates. Now tell me what is going to happen if you on already oppened N-MOSFET at "left" side of load, you open P-MOSFET at the same "left" side of load during writtes not within the same cycle (so write for closing N-MOS is delayed)?

Yeah, nah. You already explained what happens when you switch the FETs in the opposite order of what I suggested. I cannot be bothered to write about dead time for the 3rd time in this thread, but I'll leave it to this random video.

OTOH, OP seemed to indicate that he controls two H-bridges via 4 IO lines; if he does, the motor driver probably already takes care of safe switching.

[djixon]

@MicroController Sure, single full H-bridge has 4 gates. However in motor you have at least two coils so if each is controlled by full H-bridge that would mean 8 lines. If he has only 4, then yes, that means the vertical pairs are already handled by driver (as inverted) and a such mistake is not allowed by driver itself.