What would you like to see in The Next Chip?
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What would you like to see in The Next Chip?
So yeah, as you know, Espressif as such is not a company that likes resting on its laurels: we are always looking for the future of IoT chips, adding innovative features we think will do well in the market. However, we also know that the hardware and software guys/gals/... actually using our silicon may have better ideas than what we can come up with. So here's the chance to tell us about that feature you were missing in the current ESP32, that irritating hardware thing you really want to see done differently, that peripheral that's so awesome you would like to have 10 of them in a chip, maybe different voltage ranges, an integrated H-bridge, etcetera.
Some rules: While you're free to spout any idea here, crazy as it may seem, keep in mind we're not all of a sudden going to change our market: a quad-core I7-class desktop CPU, an integrated GPU or gigabytes of memory probably aren't going to happen. Think of something you would still run FreeRTOS on to put in embedded devices. Also (obviously) while we will consider the ideas you post here, we make no guarantee that your awesome idea will actually end up in a next CPU.
Some rules: While you're free to spout any idea here, crazy as it may seem, keep in mind we're not all of a sudden going to change our market: a quad-core I7-class desktop CPU, an integrated GPU or gigabytes of memory probably aren't going to happen. Think of something you would still run FreeRTOS on to put in embedded devices. Also (obviously) while we will consider the ideas you post here, we make no guarantee that your awesome idea will actually end up in a next CPU.
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Re: What would you like to see in The Next Chip?
Ok, obvious ones first:
- integrated USB
- 5GhZ wifi
- more RAM
Re: What would you like to see in The Next Chip?
There are two important things missing:
Real deepsleep which restarts at the main loop without redoing an init, and a real time clock with an alarm wakeup identical to the functionality of the chip DS3231 .
If possible RF Lora 868/915 Mhz or new wifi 900 Mhz (802.11Ah).
Real deepsleep which restarts at the main loop without redoing an init, and a real time clock with an alarm wakeup identical to the functionality of the chip DS3231 .
If possible RF Lora 868/915 Mhz or new wifi 900 Mhz (802.11Ah).
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Re: What would you like to see in The Next Chip?
Some feedback; I'm not promising anything but just to set expectations:
- USB - I can't promise anything, but as long as you don't expect USB3, we'll likely have something for you.
- More ram: That's kinda hard... the largest part of the chip already is RAM, and making more of it RAM decreases yields and increases cost by a fair amount...
- 5GHz - I don't think it's a secret we're working on that.
- 'Real' deep sleep: Well, the hardware on the ESP32 already supports keeping RAM powered in deep sleep, but there's a physical limit you'll always run into, and that is that keeping RAM powered eats into the power budget by a lot. Maybe later on we can make some kind of 'hibernate' mode that saves the entire state of the CPU to flash, for true zero-power deep sleep and instant state restore... Anyway, what I'm saying is don't expect new silicon to change the status quo here; if we implement something like this, it's probably also going to support the ESP32; the issues are mostly in software.
- RTC 'identical' to DS3231: What functionality are you missing at the moment?
- 900MHz: We're keeping an eye on the developments there.
- USB - I can't promise anything, but as long as you don't expect USB3, we'll likely have something for you.
- More ram: That's kinda hard... the largest part of the chip already is RAM, and making more of it RAM decreases yields and increases cost by a fair amount...
- 5GHz - I don't think it's a secret we're working on that.
- 'Real' deep sleep: Well, the hardware on the ESP32 already supports keeping RAM powered in deep sleep, but there's a physical limit you'll always run into, and that is that keeping RAM powered eats into the power budget by a lot. Maybe later on we can make some kind of 'hibernate' mode that saves the entire state of the CPU to flash, for true zero-power deep sleep and instant state restore... Anyway, what I'm saying is don't expect new silicon to change the status quo here; if we implement something like this, it's probably also going to support the ESP32; the issues are mostly in software.
- RTC 'identical' to DS3231: What functionality are you missing at the moment?
- 900MHz: We're keeping an eye on the developments there.
Re: What would you like to see in The Next Chip?
thank you for your reply
Maybe I misunderstood the operation of the internal RTC, but I did not see a function that will generate an alarm to wakeup the ESP32 :
RTC.setAlarm (ALM1_MATCH_HOURS, second (talarm), minute (talarm), hour (talarm), 0);
900MHz is very good for the penetration of buildings!!
Question: i do not understand why AP station is limited to 3 or 5 ST stations.It's a official limitation for a own private network with only ESP32/ESP8266 modules?
This limitation implies that one can not make its own star network with more than 3/5 ST station as nodes and an AP station as gateway.
Hoping that this issue is not off topic!!!
Maybe I misunderstood the operation of the internal RTC, but I did not see a function that will generate an alarm to wakeup the ESP32 :
RTC.setAlarm (ALM1_MATCH_HOURS, second (talarm), minute (talarm), hour (talarm), 0);
900MHz is very good for the penetration of buildings!!
Question: i do not understand why AP station is limited to 3 or 5 ST stations.It's a official limitation for a own private network with only ESP32/ESP8266 modules?
This limitation implies that one can not make its own star network with more than 3/5 ST station as nodes and an AP station as gateway.
Hoping that this issue is not off topic!!!
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Re: What would you like to see in The Next Chip?
No, but that is a software thing. You can set the RTC to a certain date using (S)NTP or another method, then use mktime() to get the Unix timestamp (aka the amount of seconds since midnight 1-1-1970) of whatever date/time you want to have an alarm on, get the current Unix timestamp by calling time() and subtracting the two to get the amount of seconds to wait. Then wait that amount, using either something like vTaskDelay or deep sleep, and you're there.
WRT the AP limitation: My guess would be that this is very much a software thing. If you need this raised, feel free to start an issue on our Github.
WRT the AP limitation: My guess would be that this is very much a software thing. If you need this raised, feel free to start an issue on our Github.
- martinayotte
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Re: What would you like to see in The Next Chip?
For the USB, having both HOST and OTG modes would be nice.
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Re: What would you like to see in The Next Chip?
Great to see you are looking for feedback from your user base!
I would like to see:
- USB FS(12M) Device/Host. (HS, 480M, with internal phy if possible!)
- 5Ghz WiFi, prefferably wifi AC (i know you are already working on 5GHz which is great!)
- A package with a larger pin count, eg 48 or 64 pins.
- Built in hardware Quadrature Decoder (for connecting to a motor encoder)
- BLE 5.0 with long range extension, and higher speed mode (2mbps symbol rate), though i think the esp32's hardware should already support this..?
These are just suggestions however!
Thanks,
Lucas
I would like to see:
- USB FS(12M) Device/Host. (HS, 480M, with internal phy if possible!)
- 5Ghz WiFi, prefferably wifi AC (i know you are already working on 5GHz which is great!)
- A package with a larger pin count, eg 48 or 64 pins.
- Built in hardware Quadrature Decoder (for connecting to a motor encoder)
- BLE 5.0 with long range extension, and higher speed mode (2mbps symbol rate), though i think the esp32's hardware should already support this..?
These are just suggestions however!
Thanks,
Lucas
Re: What would you like to see in The Next Chip?
On chip 1MB RAM, 8MB Flash, 4MB psRAM (optional), on chip 40MHz and 32.768 kHz crystals, on chip antenna matching circuitry, in 28 pin wide SOIC package or 28 pin SSOP package could make ESP-32 modules unnecessary. Price in range of of 6~9 US$ would be more than acceptable.
Re: What would you like to see in The Next Chip?
Not a H/W thing as such, but backwards compatible with the IDF for ESP32, allowing us to reuse our code for the new chip.
On the H/W side, can never get to much (application-usable) RAM and on-chip flash.
On the H/W side, can never get to much (application-usable) RAM and on-chip flash.
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