Any similar instructions like push and pop on LX6/LX7 isa

[qheinal]

I want to write some assembly to test running code from the Mcus RAM. I read the Xtensa Instruction Set Architecture pdf but it seems it doesn't have push and pop instructions like arm, x86 or other platforms. Also the xtensa instruction set pdf is really confusing and thats coming from someone that read usb specs lmao. instructions with different widths along with encodings kinda annoying. Anyway is there any instructions i can use in place of push all registers and pop them after.


i want save values of stack before i modify it then restore it after im done.

push all registers
movi a2, 0xFE
movi a3, 0xED
movi a3, 0xDE
movi a4, 0xAD
pop all registers

[MicroController]

This may be helpful: https://www.cadence.com/content/dam/cad ... ummary.pdf
You don't need to worry about instruction sizes, encodings and alignments; the assembler takes care of that.

Then also e.g. https://sachin0x18.github.io/posts/demy ... tensa-isa/

Xtensa has no push/pop instructions, and no stack pointer register either.
Convention is that register a1 is used as the stack pointer, with the assembler possibly allowing you to write "sp" instead of "a1", and registers are saved on the stack via "S32I <reg>, a1, <offset>" and restored via "L32I <reg>, a1, <offset>".

There is no "push all"/"pop all" instruction. - And you usually don't want to bluntly save and restore all registers except in an ISR; note also the "call-8" windowed call ABI normally used by gcc which significantly reduces the need for code to save registers.

I'm also interested in running bits of code from RAM, mainly just for development, so that I don't have to reflash so often when quickly iterating over variants of one function.

I guess you'll have to play around a bit with memory protection to make data RAM executable.

[qheinal]

I havent tried executing from data ram but IRAM works. I had to mark iram as rwx (read write executable) in Esp32's memory.id linker file. I also made data ram executable but havent tried running code from there yet. it took me a long time to get it to work in IRAM because some instructions don't work as expected and IRAM only allows 32 bit access.

And im not using the compiler in arduino ide or platform.io im just writing the code manually in binary/hex. Because i dont know if the compiler can compile baremetal code without including dependencies as of yet.

[MicroController]

And im not using the compiler in arduino ide or platform.io im just writing the code manually in binary/hex.

You may want to consider at least using the assembler (GNU as for Xtensa comes as "xtensa-esp32-elf-as" with the IDF).

[qheinal]

Yeh running code from data ram doesnt work even if you marked as executable. Seems only IRAM addresses are valid since it works with iram. Im guessing that esp32 has physically seperate data ram and instruction ram which maybe why it cant load the instruction. it gives this error

Addr : 0x3FFB2330 <-- this address is start of the code.

13:59:18.935 -> Guru Meditation Error: Core 0 panic'ed (InstructionFetchError). Exception was unhandled.
13:59:18.935 ->
13:59:18.935 -> Core 0 register dump:
13:59:18.935 -> PC : 0x3ffb2330 PS : 0x00060e30 A0 : 0x800d20b4 A1 : 0x3ffb2250
13:59:18.935 -> A2 : 0x3ffc2d7c A3 : 0x3ffc32c8 A4 : 0x3ffb2330 A5 : 0x3ffc2d90
13:59:18.935 -> A6 : 0x3ffc3098 A7 : 0x3ffbdb8e A8 : 0x800d1ecf A9 : 0x3ffb2230
13:59:18.968 -> A10 : 0x0000000a A11 : 0x00000008 A12 : 0x00000010 A13 : 0x3ffc31f8
13:59:18.968 -> A14 : 0x00009600 A15 : 0x3ffe46c4 SAR : 0x00000018 EXCCAUSE: 0x00000002
13:59:18.968 -> EXCVADDR: 0x3ffb2330 LBEG : 0x4008675d LEND : 0x4008676d LCOUNT : 0xffffffff
13:59:18.968 ->
13:59:18.968 ->
13:59:18.968 -> Backtrace: 0x3ffb232d:0x3ffb2250 |<-CORRUPTED

[MicroController]

You're right. The TRM confirms that on the ESP32 only SRAM0 and SRAM1 are accessible via the instruction bus, SRAM2 is not.
AFAIK, the later ESP's don't have this restriction.

[ESP_Sprite]

Note that the later ESP32 chips have this restriction, but as a security add-on, not as an architectural choice: by default, ESP-IDF will mark all RAM that does not contain the programs instructions as non-executable. You can disable this in menuconfig, however.

[qheinal]

yeh but tbh the esp32 although old still has an edge on the s2 and s3. s3 doesn't have dacs or Bluetooth classic mode , s2 has 1 core, no Bluetooth and no sdio controller. I thought the s2 was dual core but i was disappointed to know it wasn't. Oh yeh and the thing that the s2 just doesn't have a fpu even though its newer.

Btw is it normal for Sense VP and Sense VN pins to read as 4095 on 3.3v input?