RISCV-ULP <--> ESP32S3 communication

DrMickeyLauer
Posts: 168
Joined: Sun May 22, 2022 2:42 pm

RISCV-ULP <--> ESP32S3 communication

Postby DrMickeyLauer » Wed Jan 03, 2024 11:30 am

Are there any push-style ways of communicating between the ULP and the main CPU available?

My idea is that I leave the ULP continually running in order to control some aspects of low importance while the main CPU is doing its tasks. If I do that, is there a way to trigger an IRQ via two connected GPIOs from either side of the fence? I know I can wake up the main CPU, but that will not do for my use case, since it's already running.

MicroController
Posts: 1735
Joined: Mon Oct 17, 2022 7:38 pm
Location: Europe, Germany

Re: RISCV-ULP <--> ESP32S3 communication

Postby MicroController » Wed Jan 03, 2024 8:05 pm


DrMickeyLauer
Posts: 168
Joined: Sun May 22, 2022 2:42 pm

Re: RISCV-ULP <--> ESP32S3 communication

Postby DrMickeyLauer » Thu Jan 04, 2024 11:04 am

Ah, many thanks, that's quite amazing! If I understand it correctly, it works by rerouting the wake up mechanism to a custom ISR. Pretty cool.

A somewhat invasive communication method for LX7->ULP is of course ulp_riscv_reset(), but if someone has more ideas for irq-based notifications, I’m all ears.

MicroController
Posts: 1735
Joined: Mon Oct 17, 2022 7:38 pm
Location: Europe, Germany

Re: RISCV-ULP <--> ESP32S3 communication

Postby MicroController » Fri Jan 05, 2024 12:55 am

Did you see issue-11188? Seems that ISRs in the ULP are possible but documentation+IDF support is still t.b.d.

DrMickeyLauer
Posts: 168
Joined: Sun May 22, 2022 2:42 pm

Re: RISCV-ULP <--> ESP32S3 communication

Postby DrMickeyLauer » Fri Jan 05, 2024 2:46 pm

Thanks, seems there is already something under review. Let's see, then.

Who is online

Users browsing this forum: vritzka and 94 guests