Writing to SPI with a transaction length > internal memory available?

expresspotato
Posts: 24
Joined: Fri May 28, 2021 1:58 pm

Writing to SPI with a transaction length > internal memory available?

Postby expresspotato » Sun Dec 24, 2023 5:06 am

Hello,

I'm flashing firmware to another chip using the ESP32. It must be done in a single transaction with the CS line held low for the entire length of the transfer. After some digging, it looks like the SPI driver can only transfer a single transaction that is smaller than the amount of heap in internal memory available. The firmware to be flashed is about 1MB and resides in SPIRAM.

Any tips on overcoming this limitation? I've tried to set the CS line low through GPIO, but the timing isn't typical of SPI and the (other) device doesn't accept the firmware.

Regards,

ESP_Sprite
Posts: 9757
Joined: Thu Nov 26, 2015 4:08 am

Re: Writing to SPI with a transaction length > internal memory available?

Postby ESP_Sprite » Sun Dec 24, 2023 6:48 am

You should be able to set the SPI_TRANS_CS_KEEP_ACTIVE flag to use multiple transfers to get the firmware over.

Who is online

Users browsing this forum: Baidu [Spider], Bing [Bot] and 320 guests