ESP32 :: what is the max I2S parallel read frequency?

code4sex
Posts: 20
Joined: Tue Mar 16, 2021 12:23 pm

ESP32 :: what is the max I2S parallel read frequency?

Postby code4sex » Thu Sep 28, 2023 4:54 pm

Hi,

I'm sort of lost with the poor espressif tech documentation on ESP32.... It does not give any idea what the max frequency is @ which ESP32 I2S can read data in parallel mode (LCD/CAMERA). Is it F_CLK or F_BCK?

ESP32 datasheet only says that I2S is clocked by either PLL_F160M_CLK or configurable APLL.
In either case the clock source goes through the I2S clock divider whose minimum allowable value is 1/2 (section "12.3 The Clock of I2S Module", p.310).
In case PLL_F160M_CLK is used we come up with a max value of 80 MHz.
If we engage APLL we can can get the maximum value of (500MHz / 4) times 1/2 = 125 / 2 = 62.5 MHz (section "3.2.7 Audio PLL", p.44).

Further on section "12.3 The Clock of I2S Module" also says (quotation):
"When ESP32 I2S works in slave mode, the master must use I2Sn_CLK as the master clock and F_I2S >= 8 * F_BCK".

If so, F_BCK appears to be at least 8 times less than F_CLK and we end up with the upmost figures:
(a) F_BCK = F_CLK / 8 = 80 MHz / 8 = 10 MHz or
(b) F_BCK = F_CLK / 8 = 62.5 MHz / 8 = ~7.8 MHz

Am I getting the whole thing right that when we put ESP32 I2S in SLAVE RECV mode the external device should clock ESP32 I2S peripheral @ F_CLK = 80 MHz so that parallel data lines (D0....D15) are read @ F_BCK = 10 MHz at most and we can't read them any faster???????

Or what is the correct way of determining the max parallel read speed and clock frequency in RECV SLAVE mode???????

code4sex
Posts: 20
Joined: Tue Mar 16, 2021 12:23 pm

Re: ESP32 :: what is the max I2S parallel read frequency?

Postby code4sex » Sat Sep 30, 2023 10:26 am

Are there anyone from Espressif who knows the performance specs of their product?

ESP_Sprite
Posts: 9766
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32 :: what is the max I2S parallel read frequency?

Postby ESP_Sprite » Mon Oct 02, 2023 1:08 am

code4sex wrote:
Thu Sep 28, 2023 4:54 pm
Am I getting the whole thing right that when we put ESP32 I2S in SLAVE RECV mode the external device should clock ESP32 I2S peripheral @ F_CLK = 80 MHz so that parallel data lines (D0....D15) are read @ F_BCK = 10 MHz at most and we can't read them any faster???????
That sounds about right. Reason probably is that the slave clock is sampled using the master clock internally, so you cannot have the two be too close. If you have a clock that has a duty cycle that is very close to 50% you can probably go higher, but we can't guarantee it works.

Who is online

Users browsing this forum: No registered users and 97 guests