Memory Structure of LX6 Processor and ESP32 Board

[GolamMostafa]

Thanks for the answer. In fact,

I wished to know if there is any internal cache inside the ESP32 (apart from external 4 MB flash memory and the memory block of the cores).

[MicroController]

If you'd take a look at the TRM, you'd find the answer to your question and that whoever created the image ("ESP32MemoryStruc.png") made up most of the stuff about each CPU core having its own/seperate RAM.

[GolamMostafa]

Q1: The Mask ROM of Fig-1 contains a Boot Loader with which the Arduino IDE's uploader is compatible. It is because Espressif has an agreement with arduino.cc Company?

Q2: Assume that size of a sketch (application + FreeRTOS) is larger than the comined size of IRAM of Core0 + RAM of ESP32 but less than 4 MB (size of flash memory). For execution purposes, is the sketch is divided and is executed part by part by reading a part from flash and put into RAM for execution? After execution, is that part is put back into flash?

[ESP_Sprite]

Q1: The Mask ROM of Fig-1 contains a Boot Loader with which the Arduino IDE's uploader is compatible. It is because Espressif has an agreement with arduino.cc Company?

No. Arduino has nothing to do with it; it's an Espressif-specific protocol. The ESP32 board package for Arduino simply installs something that allows that to speak the Espressif upload protocol.

Q2: Assume that size of a sketch (application + FreeRTOS) is larger than the comined size of IRAM of Core0 + RAM of ESP32 but less than 4 MB (size of flash memory). For execution purposes, is the sketch is divided and is executed part by part by reading a part from flash and put into RAM for execution? After execution, is that part is put back into flash?

First of all, putting code back into flash is not something that is generally needed as code normally won't get modified. Second of all: this sort-of is the case. The ESP32 can transparently execute code from flash using a cache: if a certain block of code is executed but is not in cache, the ESP32 will read it from flash and put it into cache. If the cache is full, the least recently used block will be overwritten. (Note a block here would be one cache line which is 64 bytes.)

[GolamMostafa]

If the cache is full, the least recently used block will be overwritten. (Note a block here would be one cache line which is 64 bytes.)

Q1: By that cache, are you referring to I-Cache of the Core 0 which is 8 KB (Fig-1)? So, far I know that there is no cache memory outside the Core0/MPU0.

Q2: In Fig-3, I observe a 40 MHz crystal connected with ESP32. How much frequency actually goes to the LX6 Microprocessor? Does it go from this 40 MHz being processed (muultipy) by PLL or the LX6 has its own internal oscillator?

Q3: Can I think the code execution sequnece as follows?:
Uploading ----> Off-chip Flash Memory ----> ESP32's RAM ----> Core0's RAM ----> Core0's I-Cache ----> Execution Unit of Core0.