Tests and back story:
I am playing with an OV7670 camera module. This has an input clock frequency of 4MHz. For each byte of pixel data, it transitions a clock signal from low to high.
My thinking was that I would setup an interrupt handler such that each time the clock signal transitioned, I would read the 8 bits of parallel GPIO data. To test this theory, I performed a simpler test. I setup an interrupt handler that merely incremented a 32bit value to validate that my handler was being called.
My API logic was loosely as follows:
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gpio_install_isr_service(0); // Install the ISR service.
gpio_isr_handler_add(pixelClockPin, myHandler, NULL);
gpio_intr_enable(pixelClockPin);
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while(1) {
vTaskDelay(1000/portTICK_PERIOD_MS);
ESP_LOGD(tag, "Value of counter: %d", pclkCounter);
}
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static void IRAM_ATTR myHandler(void* arg) {
pclkCounter++;
}
My immediate guess is that an interrupt rate of 4MHz is too fast ... and the FreeRTOS environment is being starved. However, that doesn't *feel* right. With the thinking that the clock speed of an ESP32 is 240MHz, there should be enough capacity to execute a large number of instructions between interrupts at this rate.ets Jun 8 2016 00:22:57
rst:0x8 (TG1WDT_SYS_RESET),boot:0x1b (SPI_FAST_FLASH_BOOT)
Does anyone have any thoughts on this puzzle?
Neil