ESP32S3 DMA - What is a "frame"

[esp_programmer]

Hi,

Apologies for the length of this question. Feel free to read the end questions first...

I am looking at implementing an in-link DMA channel in the S3. The sending device bursts data out and I need to process it as it comes in in blocks to avoid the memory from overflowing.

The TRM has somewhat contradictory information about how the descriptors and interrupts work. It generally seems to imply that the EOF bit in a descriptor signals the end of a transfer and the next descriptor address is set to 0:

suc_eof (DW0) [30]: Specifies whether this descriptor is the last descriptor in the list.

Software clears suc_eof bit in receive descriptors. When a frame or packet has been received, this bit in
the last receive descriptor is set by hardware, and this bit in the last transmit descriptor is set by software

and:

Next descriptor address (DW2): Address of the next descriptor. If the current descriptor is the last one
(suc_eof = 1), this value is 0.

So this sort-of suggests sw defines the end of a transaction by setting the "next" address to 0, which would limit us to just the one interrupt during a transaction. But there are 2 interrupt types:

• GDMA_IN_SUC_EOF_CHn_INT: Triggered when the suc_eof bit in a receive descriptor is 1 and the data
corresponding to this receive descriptor has been received (i.e. when the data frame or packet
corresponding to an inlink has beeen received) via receive channel n.
• GDMA_IN_DONE_CHn_INT: Triggered when all data corresponding to a receive descriptor have been
received via receive channel n

This seems to indicate you can get an interrupt in the middle of a transaction and an interrupt at the very end (presumably defined by the "next" address?).

So my basic questions are:

1. Can I set the DMA controller to start, and then interrupt periodically on each block of bytes received?
2. If the answer to 1 is no, what is the intended way to deal with data AS IT COMES IN? Is it by reconfiguring and restarting the DMA controller in the ISR of each block (which might take a while...)? Or do we have to settle for using external ram and process entire transactions?

Thanks
esp_programmer

[esp_programmer]

I have just clicked that when it says "When a frame or packet has been received, this bit in
the last receive descriptor is set by hardware", it means whatever peripheral (SPI, LCD etc) is sending via the DMA will control this bit.

So it seems that you can set the system to continuously interrupt on a set number of bytes received by configuring the peripheral to do so. E.g. you can set the LCD peripheral's LCD_CAM_CAM_REC_DATA_BYTELEN to make the DMA EOF interrupt fire continuously at a given block size.

Assuming this is true, I would still like to understand the difference between the 'DONE" and "EOF" interrupts and get confirmation that my understanding of "on-the-fly" processing is as intended.

Thanks
esp_programmer

[ESP_wangning]

Hi there,

Your basic understanding about receive descriptors is correct. The EOF bit in receive descriptors depends on the data to be received: If there is a EOF flag in the data to be received, the EOF bit in receive descriptors will be automatically written to 1 by software. Users can not directly configure the EOF bit in receive descriptors.

Regarding EOF interrupts and DONE interrupts, the DONE interrupt is generated when all data corresponding to a receive descriptor has been received, while the EOF interrupt is generated when the EOF bit is 1 and all data corresponding to the receive descriptor has been received (which means that the receive descriptor is the last one in the inlink).

[esp_programmer]

Hi ESP_wangning, thanks for the reply.

The EOF bit in receive descriptors depends on the data to be received: If there is a EOF flag in the data to be received, the EOF bit in receive descriptors will be automatically written to 1 by software. Users can not directly configure the EOF bit in receive descriptors.

I'm still a little confused by this. The TRM actually states the EOF bit is set by hardware. I interpreted this to mean a peripheral (e.g. SPI) somehow signals the DMA controller when the bit needs to be written in the descriptor.

Regarding EOF interrupts and DONE interrupts, the DONE interrupt is generated when all data corresponding to a receive descriptor has been received, while the EOF interrupt is generated when the EOF bit is 1 and all data corresponding to the receive descriptor has been received (which means that the receive descriptor is the last one in the inlink).

Does this mean the DONE interrupt (if enabled) will fire on every descriptor received, regardless of EOF bit state?

Thanks

[ESP_wangning]

Hi esp_programmer,

Sorry for causing confusion by my silly typo

I'm still a little confused by this. The TRM actually states the EOF bit is set by hardware. I interpreted this to mean a peripheral (e.g. SPI) somehow signals the DMA controller when the bit needs to be written in the descriptor.

Yes, it should be hardware, and you are correct that EOF in the receive descriptors is determined by peripherals.

Does this mean the DONE interrupt (if enabled) will fire on every descriptor received, regardless of EOF bit state?

Yes!

[esp_programmer]

Ok, thanks ESP_wangning.