Instruction-fetch behaviour: undefined byte in 2-byte instructions

[Graggi]

Hi,

Chapter 3.5.4.1 Little-Endian Fetch Semantics of the Xtensa Instruction Set Architecture (ISA) Summary [1] provides some example code on its behaviour. One of the comments states:

"-- now have a 24-bit instruction (8 bits undefined if 16-bit), break it into fields"

If I replace the op-code of a 2-byte instruction with the op-code of a 3-byte instruction, would the processor take the first byte of the next instruction as the third byte of the current (former 2-byte) instruction? (That is the behaviour that x86 processors would show in this situtation.)

[1] https://esp32.com/download/file.php?id=10134

Regards

[MicroController]

Are we talking self-modifying code?

If so, from what I gather from the information available, the Xtensa is not very supportive of that. Specifically, AFAICT it provides no means to flush the instruction (prefetch) pipeline. So if and when a write to IRAM becomes "visible" to the instruction decoder depends on whether or not the corresponding location is already prefetched or not.