ESP32-GATEWAY_Rev_G - Programming via JTAG and JLink-Pro

[Accept86]

Hi,
I tried to implement an custom UART0-interrupt driver into my application software, and now have issues resetting the Board for programming it via UART0 Terminal.

Now I try via JTAG:
I connected 6 Pins between JLink-Pro and ESP32-GATEWAY_Rev_G connector header as listed in https://github.com/OLIMEX/ESP32-GATEWAY ... _Rev_G.pdf

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GND	 	P	Ground Ground also to JLINK Debugger
3V3		P	Power supply Power supply also to JLINK Debugger
IO14		I/O	MTMS to JLINK Debugger
IO12		I/O	MTDI to JLINK Debugger
IO13	 	I/O	MTCK to JLINK Debugger
IO15	 	I/O	MTDO to JLINK Debugger

I also used the freeware zadig-2.7.exe to replace my Jlink driver with a standard driver.

Then I added following files manually, that I had to script for JLINK, due to not being able finding exact examples:

C:\ESPIDF_Tools\tools\openocd-esp32\v0.11.0-esp32-20221026\openocd-esp32\share\openocd\scripts\board\esp32-gateway_own.cfg

# SPDX-License-Identifier: GPL-2.0-or-later
#
# Example OpenOCD configuration file for ESP32 connected via J-Link Plus
#
# For example, OpenOCD can be started for ESP32 debugging on
#
# openocd -f board/esp32-gateway_own.cfg
#
# Source the JTAG interface configuration file

set CHIPNAME esp32
set ESP32_FLASH_VOLTAGE none
set _RTOS "FreeRTOS"
#set ESP32_ONLYCPU 1 no single core debugging
adapter speed 5000

# Source the JTAG interface configuration file
source [find ./interface/jlink.cfg]

# Source the ESP32 configuration file
source [find ./target/esp32.cfg]

C:\ESPIDF_Tools\tools\openocd-esp32\v0.11.0-esp32-20221026\openocd-esp32\share\openocd\scripts\interface\jlink.cfg

# SPDX-License-Identifier: GPL-2.0-or-later
#
# SEGGER J-Link
#
# http://www.segger.com/jlink.html
#
adapter driver jlink

#adapter list

adapter speed 5000

I tried to repair my bootloader for testing issues and my application with command line arguments such as following, after starting the esp.idf context:

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openocd -f "board/esp32-gateway_own.cfg" -c "program build/bootloader/bootloader.elf erase unlock verify reset exit 0x1000"

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openocd -f "board/esp32-gateway_own.cfg" -c "program build/tcp_client_multiple.elf verify reset exit 0x8000"

But it doesnt seem to work - i get outputs like:

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C:\wrs12\03_Software\IWolfLink_Redesign\ESP32_WiFi_FW_WolfLink>openocd -f "board/esp32-gateway_own.cfg" -c "program build/bootloader/bootloader.elf erase unlock verify reset exit 0x1000"
Open On-Chip Debugger v0.11.0-esp32-20221026 (2022-10-26-14:48)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
Info : J-Link V10 compiled Jul 22 2022 11:40:29
Info : Hardware version: 10.10
Info : VTarget = 3.277 V
Info : clock speed 5000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : starting gdb server for esp32.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
Info : [esp32.cpu0] Target halted, PC=0x40000400, debug_reason=00000000
Info : [esp32.cpu0] Reset cause (3) - (Software core reset)
Info : Set GDB target to 'esp32.cpu0'
Info : [esp32.cpu1] Target halted, PC=0x40000400, debug_reason=00000000
Info : [esp32.cpu1] Reset cause (14) - (CPU1 reset by CPU0)
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : [esp32.cpu0] requesting target halt and executing a soft reset
Info : [esp32.cpu0] Debug controller was reset.
Info : [esp32.cpu0] Core was reset.
Info : [esp32.cpu0] Target halted, PC=0x500000CF, debug_reason=00000000
Info : [esp32.cpu0] Reset cause (3) - (Software core reset)
Info : [esp32.cpu1] requesting target halt and executing a soft reset
Info : [esp32.cpu0] Core was reset.
Info : [esp32.cpu0] Target halted, PC=0x40000400, debug_reason=00000000
Info : [esp32.cpu1] Debug controller was reset.
Info : [esp32.cpu1] Core was reset.
Info : [esp32.cpu1] Target halted, PC=0x40000400, debug_reason=00000000
Info : [esp32.cpu1] Reset cause (14) - (CPU1 reset by CPU0)
Info : [esp32.cpu0] Reset cause (3) - (Software core reset)
** Programming Started **
Error: timed out while waiting for target halted
Info : [esp32.cpu0] Target halted, PC=0x4000C2F6, debug_reason=00000000
Error: xtensa_wait_algorithm: not halted 0, pc 0x4000c2f6, ps 0x60025
Error: Failed to wait algorithm (-302)!
Error: Algorithm run failed (-302)!
Error: Failed to run flasher stub (-302)!
Warn : Failed to get flash mappings (-302)!
Error: Target is already running an algorithm
Error: Failed to start algorithm (-4)!
Error: Failed to run flasher stub (-4)!
Error: Target is already running an algorithm
Error: Failed to start algorithm (-4)!
Error: Failed to run flasher stub (-4)!
Error: Failed to probe flash, size 0 KB
Error: auto_probe failed
** Programming Failed **
shutdown command invoked

One time programming worked but verifying did not, when I programmed the application with offset 0x10000