SPI: Latching MOSI and sampling MISO on the same edge

[systeera]

I have been trying to communicate with the ADS8330 ADC for a couple of days now but I can't get it to work. The problem is around the SPI-mode because no mode seems to fit this device: Regardless of what mode is being used, changing CPHA is affecting both MOSI and MISO in the same way, but this ADC is using the falling edge for sampling MOSI and the falling edge for latching MISO.

In the attached screenshot, the four waveforms are shown, from top to bottom:
1: SCLK
2: CS
3: MISO
4: MOSI

As one can see:
MISO is latched on the falling edge and thus should be sampled on the rising edge.
MOSI is latched on the rising edge and thus should be sampled on the falling edge.
SCLK is low when idle.
MISO data is ready to be sampled on the first rising edge.

According to the ESP32s3 manual:
Mode 0: CPOL = 0, CPHA = 0; SCK is 0 when the SPI is in idle state; data is changed on the negative edge of SCK and sampled on the positive edge. The first data is shifted out before the first negative edge of SCK.
Mode 1: CPOL = 0, CPHA = 1; SCK is 0 when the SPI is in idle state; data is changed on the positive edge of SCK and sampled on the negative edge.
Mode 2: CPOL = 1, CPHA = 0; SCK is 1 when the SPI is in idle state; data is changed on the positive edge of SCK and sampled on the negative edge. The first data is shifted out before the first positive edge of SCK.
Mode 3: CPOL = 1, CPHA = 1; SCK is 1 when the SPI is in idle state; data is changed on the negative edge of SCK and sampled on the positive edge.

So setting SPI-mode to 0 would result in a correct communication for MISO but wrong for MOSI, whereas setting SPI-mode to 1 would result in a correct communication for MOSI but wrong for MISO. This is indeed true and matches real world tests with trying out to communicate with the chip.

SPI-mode is currently set to 1 and I can see the ADC is receiving configuration data correctly but since it's wrong for MISO, I am reading the data half a clock cycle too late and the data gets corrupt. The test signal is around value 0x7fff whereas I'am reading a value around 0xffff.

If I set the mode to 0, the ADC can't interpret my configuration command to sample only one channel, so even if the configuration gets wrong, it will spit out ADC data. In this way I can see in software that I receive the correct sampling value around 0x7fff but every other value is from the wrong channel.

The behaviour I am seeking is:
* Latch data on MOSI on the rising edge
* Sample data on MISO on the rising edge

How can I configure the ESP32 to do this? I am using ESP32s3 chip with ESP-IDF v 5.0, SPI2 unit.

Regards,
Manne

[systeera]

Anyone?

[ESP_Sprite]

Sorry, I'm not sure if out hardware is capable of that...