ESP32-S2 I2S Larger-than-32-bit word sizes

[cnlohr]

I have a situation where I need to output a WS clock that is over a cadence of 512 bits not 32- or 64- per flip. Is there some mechanism that can be used to provide a WS clock that is of a wider bit width?

One idea I had was to use the I2S engine in duplex mode, and shift out the "ideal" WS, but that feels really janky and dangerous.

I have attached an example of a TDM256 that was included. I hope there's some way to extend the functional value in rx_bits_mod via a divisor or something.

[ESP_Sprite]

The S2 doesn't support TDM; I think we added it on the S3/C3, so technically switching to those chips would be an option. I imagine you may not have that freedom, though. Using the duplex Tx sounds like a viable option to 'fake' the ws signal; another option I could imagine is to loop back the WS signal to something like a SPI slave or perhaps the MCPWM peripheral (not sure if that has the capabilities) to act like an ad-hoc divider, but I think that'd be more janky.

[cnlohr]

I could, but it would be very difficult to make this work without the APLL, which as far as I understand has been dropped from the S3 :-/.

It may be worth fabbing up an S3 board to give it a shot to see if I can make it work with a clunkier clock.

I will just try to duplex it. At least as of yesterday I was struggling with that.