For a project I’m using an SPI ADC with DMA. It’s a 12-bit ADC (the MCP33141). The CNVST pin of the ADC is used to trigger a new conversion on the rising edge. When the conversion is complete this pin has to be lowered to read the ADC value. So in addition to being used to start the ADC conversion, it’s also used as a chip select. Seems simple… But to get samples fast enough I have to use DMA. I haven’t found a way to tell DMA to raise the CNVST after every 12 bits, pause the clock, wait a few ns, lower CVNST and resume the clock.
For now I’ve come up with the idea to generate a PWM signal that sets the CNVST high after every 12 bits. The bits that get received after the CVNST was set high will be disposed of because their place in the buffer should be predictable. At lower speeds this idea seems to work alright, but at higher speeds the SPI clock starts too late in comparison to the PWM signal. The image below illustrates the issue:
So far I’ve tried a few things but I haven’t found anything that’s really helping. I thought the MCPWM peripheral could help me because it offers a sync module, but that only seems to work when the signal you’re syncing to has a lower frequency than the one you’re generating, which is not the case here…
I also tried using the Pulse Counter and toggling the CNVST pin in the interrupt but that was also too slow.
As a last resort I even tried using logic chips, so a counter and a few gates, to generate the CNVST signal from the SPI clock. However the speed was also quite limited because I suspect that the rise and fall times of those IC’s weren’t good enough. The results were at least no where near the results that I got when I used an FPGA to generate the signal. With the logic chips I was only able to handle an SPI clock of few MHz. The FPGA was near 20MHz. But even if those chips would have worked, I would still prefer a solution without any additional hardware.
I hope someone is able to help me with this : ).