How to allocate PSRAM for only one CPU core on ESP32 Xtensa

[QlifeDeveloper]

Hi
I need to reserve one CPU core for critical interrupt and WIFI handling.
When I use PSRAM the CPU core accessing the PSRAM will get stalled until PSRAM data transmission is concluded.
How can I configure ESP-IDF to only allocate PSRAM for one CPU core so the other CPU core won't get stalled due to PSRAM access?
Thanks in advance!
Best regards Søren

[ESP_Sprite]

PSRAM access by itself doesn't stall both cores, only the core that is affected. However, what you may be seeing is that PSRAM and flash use the same bus, and as such the processor not using psram will be stalled on a cache miss as it needs to wait for the PSRAM access to finish before it can do a flash access.

[QlifeDeveloper]

PSRAM access by itself doesn't stall both cores, only the core that is affected. However, what you may be seeing is that PSRAM and flash use the same bus, and as such the processor not using psram will be stalled on a cache miss as it needs to wait for the PSRAM access to finish before it can do a flash access.

Thanks for your input.
My concern is that any cache miss in the PSRAM stalls the core. My timing constraints does not leave time for the core to stall for the time period it takes to access PSRAM. I need to assign one core for handling timing critical functionality which does not access PSRAM.
Best regards Søren

[ESP_Sprite]

The only solution to that would be to make sure that any time-critical code you have runs entirely (including any functions it calls) in IRAM.

(Also, what are you doing that requires timing that tight? Are you sure you can't handle it in hardware, with e.g. the RMT peripheral?)

[QlifeDeveloper]

Hi
Thanks for your replies
Is it correct that a cache miss in the PSRAM area just triggers functionality implemented in the Espressif "spiram_psram.c" module?
And thereby only stalls the current thread accessing the PSRAM?
Thanks in advance!
Best regards Søren

[ESP_Sprite]

No, it does not trigger any software routine; cache misses are handled in hardware. As such, they will stall the entire core that does the read; hardware is not aware of threading.