Hi.
I have created a sketch that allocates memory and then links up DMA descriptors so that it loops forever. When I try to do this using PSRAM as the DMA buffer, I get garbage output.
Refer to live example here:
https://github.com/mrfaptastic/esp32s3-hub75-psram
Any ideas? Is this some cache issue again? How do I work around this when outputting continuously?
ESP32-S3: Continuous DMA from PSRAM via. LCD produces garbage.
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Re: ESP32-S3: Continuous DMA from PSRAM via. LCD produces garbage.
Might very well be the case indeed; if the CPU writes to those PSRAM buffers, you need to poke the cache to have it write back that to the PSRAM first.
Re: ESP32-S3: Continuous DMA from PSRAM via. LCD produces garbage.
Could I write to the PSRAM using DMA from SRAM?
Would that get around the issue of trying to change bytes directly from the PSRAM malloc?
Would that get around the issue of trying to change bytes directly from the PSRAM malloc?
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- Posts: 9739
- Joined: Thu Nov 26, 2015 4:08 am
Re: ESP32-S3: Continuous DMA from PSRAM via. LCD produces garbage.
You can, but it's probably easier to writeback the cache using Cache_WriteBack_Addr() (from rom/cache.h) after you're don writing it.
Re: ESP32-S3: Continuous DMA from PSRAM via. LCD produces garbage.
Thanks for this. Got it to work after calling this function.
Re: ESP32-S3: Continuous DMA from PSRAM via. LCD produces garbage.
I notice now that if I try use a clock divider less than 4 with PSRAM it fails to provide an output, but can use a clock divider of up down to 2 with the SRAM when using the LCD peripheral.
Any ideas why? I have an S3 with Octal SPIRAM.
Any ideas why? I have an S3 with Octal SPIRAM.
Code: Select all
// LCD_CAM_LCD_CLK_SEL Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK. (R/W)
LCD_CAM.lcd_clock.lcd_clk_sel = 2;
LCD_CAM.lcd_clock.lcd_ck_out_edge = 0; // PCLK low in 1st half cycle
LCD_CAM.lcd_clock.lcd_ck_idle_edge = 0; // PCLK low idle
LCD_CAM.lcd_clock.lcd_clk_equ_sysclk = 0; // PCLK = CLK / (CLKCNT_N+1)
if (_cfg.psram_clk_hack) // fastest speed I can get PSRAM to work before nothing shows
{
LCD_CAM.lcd_clock.lcd_clkm_div_num = 4;
}
else
{
//LCD_CAM.lcd_clock.lcd_clkm_div_num = lcd_clkm_div_num;
LCD_CAM.lcd_clock.lcd_clkm_div_num = 3;
}
ESP_LOGI(TAG, "Clock divider is %d", LCD_CAM.lcd_clock.lcd_clkm_div_num);
LCD_CAM.lcd_clock.lcd_clkm_div_a = 1; // 0/1 fractional divide
LCD_CAM.lcd_clock.lcd_clkm_div_b = 0;
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- Posts: 9739
- Joined: Thu Nov 26, 2015 4:08 am
Re: ESP32-S3: Continuous DMA from PSRAM via. LCD produces garbage.
I don't have the calculations at hand here, but it's possibly a bandwidth issue; PSRAM (even octal) has less bandwidth than internal RAM and you may be saturating the bus.
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