【已解决】ESP32S3 程序读取flash出错，读出来全是0xFF

[xinhaojie]

开发板 ： ESP32-S3-DevKitC-1 v1.1 R8N32版本 采购于官方淘宝店，预计使用半年左右。
软件环境 IDF 4.4.2+VSCODE

最近在测试程序的是有一直出现莫名其妙的问题。今天使用flash_encryption 这个测试用例。我在spi_flash_read接口测试前加上了spi_flash_write测试，想把值再次写入一下。下面是测试结果，使用esp_partition_read和spi_flash_read接口读取出来的全是0xFF。麻烦官方给看下是怎么回事吧。是新版本的问题，还是我硬件的问题。

为了方便定位问题，我把efuse也读取出来贴出来了。

--------------------------------------------------efuse 值-----------------------------------------------------------------------
Connecting....
Detecting chip type... ESP32-S3
espefuse.py v3.3.2-dev

=== Run "summary" command ===
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Config fuses:
DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0)
DIS_DCACHE (BLOCK0) Disables DCache = False R/W (0b0)
DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0)
DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0)
DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0)
DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0)
DIS_APP_CPU (BLOCK0) Disables APP CPU = False R/W (0b0)
FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0)
unit is (ms/2). When the value is 15, delay is 7.
5 ms
DIS_DIRECT_BOOT (BLOCK0) Disables direct boot mode = False R/W (0b0)
DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Disables USB-Serial-JTAG ROM printing = False R/W (0b0)
FLASH_ECC_MODE (BLOCK0) Configures the ECC mode for SPI flash
= 16-byte to 18-byte mode R/W (0b0)
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Disables USB-Serial-JTAG download feature in UART = False R/W (0b0)
download boot mode
UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00)
FLASH_TYPE (BLOCK0) Selects SPI flash type = 8 data lines R/W (0b1)
FLASH_PAGE_SIZE (BLOCK0) Sets the size of flash page = 0 R/W (0b00)
FLASH_ECC_EN (BLOCK0) Enables ECC in Flash boot mode = False R/W (0b0)
FORCE_SEND_RESUME (BLOCK0) Forces ROM code to send an SPI flash resume comman = False R/W (0b0)
d during SPI boot
DIS_USB_OTG_DOWNLOAD_MODE (BLOCK0) Disables USB-OTG download feature in UART download = True R/W (0b1)
boot mode
BLOCK_USR_DATA (BLOCK3) User data
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W

Efuse fuses:
WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000)
RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000)

Identity fuses:
SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000)
ure)
MAC (BLOCK1) Factory MAC Address
= 7c:df:a1:e1:10:c4 (OK) R/W
WAFER_VERSION (BLOCK1) WAFER version = 1 R/W (0b001)
PKG_VERSION (BLOCK1) ??? Package version = ESP32-S3 R/W (0x0)
BLOCK1_VERSION (BLOCK1) ??? BLOCK1 efuse version = 1 R/W (0b001)
OPTIONAL_UNIQUE_ID (BLOCK2) ??? Optional unique 128-bit ID
= 49 58 74 f6 88 43 ba b7 e2 13 04 5f cd de 0c eb R/W
BLOCK2_VERSION (BLOCK2) ??? Version of BLOCK2 = 3 R/W (0b011)
CUSTOM_MAC (BLOCK3) Custom MAC Address
= 00:00:00:00:00:00 (OK) R/W

Security fuses:
SOFT_DIS_JTAG (BLOCK0) Software disables JTAG by programming odd number o = 0 R/W (0b000)
f 1 bit(s). JTAG can be re-enabled via HMAC periph
eral
HARD_DIS_JTAG (BLOCK0) Hardware disables JTAG permanently = False R/W (0b0)
DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0)
des
SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000)
t mode is set. Enabled when 1 or 3 bits are set,di
sabled otherwise
SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revokes use of secure boot key digest 0 = False R/W (0b0)
SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revokes use of secure boot key digest 1 = False R/W (0b0)
SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revokes use of secure boot key digest 2 = False R/W (0b0)
KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0)
KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0)
KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0)
KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0)
KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0)
KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0)
SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0)
SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0)
STRAP_JTAG_SEL (BLOCK0) Enable selection between usb_to_jtagor pad_to_jtag = False R/W (0b0)
through GPIO3
DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0)
ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0)
h only)
BLOCK_KEY0 (BLOCK4)
Purpose: USER
Encryption key0 or user data
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_KEY1 (BLOCK5)
Purpose: USER
Encryption key1 or user data
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_KEY2 (BLOCK6)
Purpose: USER
Encryption key2 or user data
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_KEY3 (BLOCK7)
Purpose: USER
Encryption key3 or user data
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_KEY4 (BLOCK8)
Purpose: USER
Encryption key4 or user data
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_KEY5 (BLOCK9)
Purpose: USER
Encryption key5 or user data
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_SYS_DATA2 (BLOCK10) System data (part 2)
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W

Spi_Pad_Config fuses:
SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000)
SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000)
SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000)
SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000)
SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000)
SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000)
SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000)
SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000)
SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000)
SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000)
SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000)

Usb Config fuses:
DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0)
USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0)
EXT_PHY_ENABLE (BLOCK0) Enables external USB PHY = False R/W (0b0)
BTLC_GPIO_ENABLE (BLOCK0) Enables BTLC GPIO = 0 R/W (0b00)
DIS_USB_JTAG (BLOCK0) Disable usb_serial_jtag-to-jtag function = False R/W (0b0)
DIS_USB_SERIAL_JTAG (BLOCK0) Disable usb_serial_jtag module = False R/W (0b0)
USB_PHY_SEL (BLOCK0) Select internal/external PHY for USB OTGand usb_se = False R/W (0b0)
rial_jtag

Vdd_Spi Config fuses:
VDD_SPI_XPD (BLOCK0) The VDD_SPI regulator is powered on = True R/W (0b1)
VDD_SPI_TIEH (BLOCK0) The VDD_SPI power supply voltage at reset = Connect to 1.8V LDO R/W (0b0)
VDD_SPI_FORCE (BLOCK0) Force using VDD_SPI_XPD and VDD_SPI_TIEH to config = True R/W (0b1)
ure VDD_SPI LDO
PIN_POWER_SELECTION (BLOCK0) Sets default power supply for GPIO33..37 = VDD_SPI R/W (0b1)

Wdt Config fuses:
WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = 0 R/W (0b00)

Flash voltage (VDD_SPI) set to 1.8V by efuse.


-----------------------------------------flash_encryption 例程运行日志-----------------------------------
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0x18 (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
Octal Flash Mode Enabled
For OPI Flash, Use Default Flash Boot Mode
mode:SLOW_RD, clock div:1
load:0x3fce3808,len:0x1654
load:0x403c9700,len:0xbb8
load:0x403cc700,len:0x2f8c
SHA-256 comparison failed:
Calculated: 662af6c1b4c9e1dd2de0bb716ec46d8a16cc538f842cb7f75514c5473a538c7e
Expected: 405e6d2b4de0d6b8d31281394ef53848dedc9f84bf1d546c666dacda9fbed504
Attempting to boot anyway...
entry 0x403c9954
I (50) boot: ESP-IDF v4.4.2-dirty 2nd stage bootloader
I (51) boot: compile time 11:45:01
I (51) boot: chip revision: 0
I (53) boot.esp32s3: Boot SPI Speed : 80MHz
I (58) boot.esp32s3: SPI Mode : SLOW READ
I (63) boot.esp32s3: SPI Flash Size : 16MB
I (68) boot: Enabling RNG early entropy source...
I (73) boot: Partition Table:
I (77) boot: ## Label Usage Type ST Offset Length
I (84) boot: 0 nvs WiFi data 01 02 0000a000 00006000
I (91) boot: 1 storage Unknown data 01 ff 00010000 00001000
I (99) boot: 2 factory factory app 00 00 00020000 00100000
I (106) boot: 3 nvs_key NVS keys 01 04 00120000 00001000
I (114) boot: End of partition table
I (118) esp_image: segment 0: paddr=00020020 vaddr=3c020020 size=0823ch ( 33340) map
I (134) esp_image: segment 1: paddr=00028264 vaddr=3fc90e30 size=0271ch ( 10012) load
I (138) esp_image: segment 2: paddr=0002a988 vaddr=40374000 size=05690h ( 22160) load
I (150) esp_image: segment 3: paddr=00030020 vaddr=42000020 size=19820h (104480) map
I (177) esp_image: segment 4: paddr=00049848 vaddr=40379690 size=0779ch ( 30620) load
I (185) esp_image: segment 5: paddr=00050fec vaddr=50000000 size=00010h ( 16) load
I (191) boot: Loaded app from partition at offset 0x20000
I (191) boot: Disabling RNG early entropy source...
I (205) cpu_start: Pro cpu up.
I (206) cpu_start: Starting app cpu, entry point is 0x403750f4
0x403750f4: call_start_cpu1 at D:/software/Espressif/frameworks/esp-idf-v4.4.2/components/esp_system/port/cpu_start.c:160

I (0) cpu_start: App cpu up.
I (220) cpu_start: Pro cpu start user code
I (220) cpu_start: cpu freq: 160000000
I (220) cpu_start: Application information:
I (222) cpu_start: Project name: flash_encryption
I (228) cpu_start: App version: 1
I (233) cpu_start: Compile time: Sep 7 2022 11:44:38
I (239) cpu_start: ELF file SHA256: 010dff40c924a7d3...
I (245) cpu_start: ESP-IDF: v4.4.2-dirty
I (250) heap_init: Initializing. RAM available for dynamic allocation:
I (257) heap_init: At 3FC93F60 len 0004C0A0 (304 KiB): D/IRAM
I (264) heap_init: At 3FCE0000 len 0000EE34 (59 KiB): STACK/DRAM
I (270) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (277) heap_init: At 600FE000 len 00002000 (8 KiB): RTCRAM
I (284) spi_flash: detected chip: mxic
W (287) spi_flash: Detected flash size > 16 MB, but access beyond 16 MB is not supported for this flash model yet.
I (298) spi_flash: flash io: dio
W (302) spi_flash: Detected size(32768k) larger than the size in the binary image header(16384k). Using the size in the binary image header.
I (316) sleep: Configure to isolate all GPIO pins in sleep state
I (323) sleep: Enable automatic switching of GPIO sleep configuration
I (330) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.

Example to check Flash Encryption status
This is esp32s3 chip with 2 CPU core(s), WiFi/BLE, silicon revision 0, 16MB external flash
FLASH_CRYPT_CNT eFuse value is 0
Flash encryption feature is disabled
Erasing partition "storage" (0x1000 bytes)
Writing data with esp_partition_write:
I (451) example: 0x3fcf3e10 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f |................|
I (451) example: 0x3fcf3e20 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f |................|
I (461) example: 0x3fcf3e30 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f | !"#$%&'()*+,-./|
I (471) example: 0x3fcf3e40 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f |0123456789:;<=>?|
Reading with esp_partition_read:
I (481) example: 0x3fcf3dd0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
I (491) example: 0x3fcf3de0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
I (501) example: 0x3fcf3df0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
I (511) example: 0x3fcf3e00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
Reading with spi_flash_write:
I (521) example: 0x3fcf3e10 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f |................|
I (531) example: 0x3fcf3e20 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f |................|
I (541) example: 0x3fcf3e30 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f | !"#$%&'()*+,-./|
I (551) example: 0x3fcf3e40 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f |0123456789:;<=>?|
Reading with spi_flash_read:
I (561) example: 0x3fcf3dd0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
I (571) example: 0x3fcf3de0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
I (581) example: 0x3fcf3df0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
I (591) example: 0x3fcf3e00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|

[ESP_igrr]

Probably this is caused by the same reason as the other issue about NVS you have reported. The flash chip has octal interface, but DIO mode is set in menuconfig. Please try enabling CONFIG_ESPTOOLPY_OCT_FLASH.

[xinhaojie]

根据您的提示，设置后确实可以使用了。我同时测试了QIO 模式，8线spi会报错重启。

Probably this is caused by the same reason as the other issue about NVS you have reported. The flash chip has octal interface, but DIO mode is set in menuconfig. Please try enabling CONFIG_ESPTOOLPY_OCT_FLASH.

[ESP_igrr]

That sounds about right. Octal flash is usually incompatible with DIO and QIO modes, so if your module has octal flash, you have to enable specifically that mode.