ESP32S3 DMA - What is a "frame"
Posted: Sat Jul 15, 2023 4:58 am
Hi,
Apologies for the length of this question. Feel free to read the end questions first...
I am looking at implementing an in-link DMA channel in the S3. The sending device bursts data out and I need to process it as it comes in in blocks to avoid the memory from overflowing.
The TRM has somewhat contradictory information about how the descriptors and interrupts work. It generally seems to imply that the EOF bit in a descriptor signals the end of a transfer and the next descriptor address is set to 0:
So my basic questions are:
1. Can I set the DMA controller to start, and then interrupt periodically on each block of bytes received?
2. If the answer to 1 is no, what is the intended way to deal with data AS IT COMES IN? Is it by reconfiguring and restarting the DMA controller in the ISR of each block (which might take a while...)? Or do we have to settle for using external ram and process entire transactions?
Thanks
esp_programmer
Apologies for the length of this question. Feel free to read the end questions first...
I am looking at implementing an in-link DMA channel in the S3. The sending device bursts data out and I need to process it as it comes in in blocks to avoid the memory from overflowing.
The TRM has somewhat contradictory information about how the descriptors and interrupts work. It generally seems to imply that the EOF bit in a descriptor signals the end of a transfer and the next descriptor address is set to 0:
and:suc_eof (DW0) [30]: Specifies whether this descriptor is the last descriptor in the list.
Software clears suc_eof bit in receive descriptors. When a frame or packet has been received, this bit in
the last receive descriptor is set by hardware, and this bit in the last transmit descriptor is set by software
So this sort-of suggests sw defines the end of a transaction by setting the "next" address to 0, which would limit us to just the one interrupt during a transaction. But there are 2 interrupt types:Next descriptor address (DW2): Address of the next descriptor. If the current descriptor is the last one
(suc_eof = 1), this value is 0.
This seems to indicate you can get an interrupt in the middle of a transaction and an interrupt at the very end (presumably defined by the "next" address?).• GDMA_IN_SUC_EOF_CHn_INT: Triggered when the suc_eof bit in a receive descriptor is 1 and the data
corresponding to this receive descriptor has been received (i.e. when the data frame or packet
corresponding to an inlink has beeen received) via receive channel n.
• GDMA_IN_DONE_CHn_INT: Triggered when all data corresponding to a receive descriptor have been
received via receive channel n
So my basic questions are:
1. Can I set the DMA controller to start, and then interrupt periodically on each block of bytes received?
2. If the answer to 1 is no, what is the intended way to deal with data AS IT COMES IN? Is it by reconfiguring and restarting the DMA controller in the ISR of each block (which might take a while...)? Or do we have to settle for using external ram and process entire transactions?
Thanks
esp_programmer