ESP32 Forum

Hi,

Chapter 3.2 Processor-Configuration Parameters of the Xtensa Instruction Set Architecture (ISA) Summary [1] reads as follows:

"Core Processor-Configuration Parameters lists the processor-configuration parameters that are required in the core architecture. Additional processor-configuration parameters are listed with each option described in Architectural Options on page 73.

Table 5: Core Processor-Configuration Parameters

Parameter : msbFirst
Description: Byte order
Valid Values: 0 or 1
0 → Little-endian (least significant bit first)
1 → Big-endian (most significant bit first)"

Is this setting hardcoded into the chip or is it somehow changeable?

Best regards

[1] https://esp32.com/download/file.php?id=10134

Yes. It's configuration for the IP, as in we can set it at design time, but by the time you have the actual chip in your hands it's fixed.

Hi,

thanks for the quick answer.

GCC offers two flags to specify the endianness of the binary to build [1]: -mbig-endian and -mlittle-endian. Searching within the ESP-IDF with
> grep -rnw ./esp-idf -e "-mbig-endian" (resp. "-mlittle-endian")
did not provide any results.

When compiling the Hello World example project with default settings and using xtensa-esp32-elf-objdump[2] to analyse the ELF-Binary I get the following result:

> xtensa-esp32-elf-objdump -h hello_world.elf
file format elf32-xtensa-le

Can little-endian be considered the "default-case"?

One follow-up question: As quoted above the description for msbFirst only reads "Byte order". In which cases is the byte order influenced by this setting? Data streams? Data within memory? Constants within instructions? Registervariables within instructions? Op-code placement?

[1] https://gcc.gnu.org/onlinedocs/gcc-3.3. ... tions.html
[2] https://github.com/badgeteam/xtensa-esp32-elf

Regards

No clue. (It's not super-relevant for me either as I don't think I'll ever run into a big-endian Xtensa processor, to be honest)