ESP32 TRM: I2C interrupt flags
Posted: Sat Mar 04, 2023 11:25 am
I just noticed that the I2C interrupt status/mask/enable bits documented in the ESP32 TRM v4.8 do not match the definitions in soc/i2c_reg.h, like, at all.
I failed to see that the right-most bit of the registers' diagrams is supposed to be bit #3 and bit #5 is the one just left of #3
