ESP32 Forum

Hi,

I am trying to use the ESP32-S2 SPI3 unit for a bit of an odd application, and I *think* it can do what I need. However, there are a few things in the technical manual that are very much not clear, and I would love to get some clarifications.

I was planning to use segmented DMA for my application. These are the corner cases that I cannot really figure out:

1. In full-duplex mode, what happens if SPI_USR_MOSI_DBITLEN and SPI_USR_MISO_DBITLEN differ? This is relevant because sometimes my application will have data flowing full duplex, and sometimes not... and it would be annoying to have to allocate memory that will be just thrown out.

2. What are the semantics of SPI_Q_POL? If one sets SPI_Q_POL = 0 and SPI_USR_MOSI = 0, will MOSI contain all zeroes?

3. Similarly, if SPI_USR_MISO = 0. is input discarded as opposed to send to DMA or the buffer registers?

4. For (2) and (3), does setting either of those bits also require SPI_DOUTDIN = 0?

5. If SPI_CSx_DIS = 1, what is the signal present on the CS# output pin?

6. Can an unused DMA descriptor be empty (size = length = 0), or does that require the descriptor to be skipped over in the linked list?

7. When *_DBITLEN+1 is *not* a multiple of 8, does that mean that the remaining bits are left in a FIFO somewhere and that a subsequent transaction can continue where it left off in the bitstream (the TRM seems to imply it, but it isn't clear if that applies only to whole bytes or not), or are any such fractional bytes discarded/zero-padded/filled with garbage?

8. What are one expected to put into SPI_CONF_BITLEN? The TRM says to "pay attention to it", but at least I cannot find any description of what values one can put there (specifically, what value would represent the minimum latency?)

Many thanks,
-hpa

Oh, and:

9. Is there a way to explicitly set (bitbang) the state of the MOSI and SCLK (presumably CS# is triival) during the IDLE phase?

Thanks again,

-hpa

I can't answer your questions directly, but I've made an internal issue with the documentation team; if they squirrel out the answers we'll reply here.

Digital team answered:

Q1. In full-duplex mode, what happens if SPI_USR_MOSI_DBITLEN and SPI_USR_MISO_DBITLEN differ? This is relevant because sometimes my application will have data flowing full duplex, and sometimes not... and it would be annoying to have to allocate memory that will be just thrown out.

Answer: In this case, SPI_USR_MOSI_DBITLEN is valid.



Q2. What are the semantics of SPI_Q_POL? If one sets SPI_Q_POL = 0 and SPI_USR_MOSI = 0, will MOSI contain all zeroes?

Answer: It can be seen in https://www.espressif.com.cn/sites/defa ... ual_en.pdf Register 24.8: SPI_CTRL_REG (0x0008).

SPI_Q_POL: The bit is used to set MISO line polarity when there is no data transfer in MISO line.

SPI_D_POL: The bit is used to set MOSI line polarity when there is no data transfer in MOSI line.

In master mode, MOSI line is driven by GP-SPI when GP-SPI is idle. If one sets SPI_Q_POL = 0 and SPI_USR_MOSI = 0, MOSI contains all zeroes when GP-SPI is idle. When GP-SPI sends data out, MOSI line contains the real serial data.



Q3. Similarly, if SPI_USR_MISO = 0. is input discarded as opposed to send to DMA or the buffer registers?

Answer: In full-duplex mode, GP-SPI will receive and send data at the same time, which is not controlled by SPI_USR_MISO and SPI_USR_MOSI.

In master half-duplex mode, when SPI_USR_MISO = 0, the input is discarded.

In master half-duplex mode, when SPI_USR_MOSI = 0, there is no valid data sent out.



Q4. For (2) and (3), does setting either of those bits also require SPI_DOUTDIN = 0?

Answer: When SPI_DOUTDIN =0 in master mode, GP-SPI is in master half-duplex mode;

When SPI_DOUTDIN =1 in master mode, GP-SPI is in master full-duplex mode.

The detail can be seen in Chapter 24.4.3 and Chapter 24.4.4 of https://www.espressif.com.cn/sites/defa ... ual_en.pdf



Q5. If SPI_CSx_DIS = 1, what is the signal present on the CS# output pin?

Answer: GP-SPI2 has 6 slave chip select signal SPI_CS0~5. When SPI_CSx_DIS = 1, the value of SPI_CSx is 1, the relative slave is not active.



Q6. Can an unused DMA descriptor be empty (size = length = 0), or does that require the descriptor to be skipped over in the linked list?

Answer: No



Q7. When _DBITLEN+1 is *not a multiple of 8, does that mean that the remaining bits are left in a FIFO somewhere and that a subsequent transaction can continue where it left off in the bitstream (the TRM seems to imply it, but it isn't clear if that applies only to whole bytes or not), or are any such fractional bytes discarded/zero-padded/filled with garbage?

Answer: It is recommended that the transfer data unit is byte. If (8*n+i) bits (0<i<8) is transferred, the extra i-bits may be discarded. The detail will be shown in TRM soon.



Q8. What are one expected to put into SPI_CONF_BITLEN? The TRM says to "pay attention to it", but at least I cannot find any description of what values one can put there (specifically, what value would represent the minimum latency?)

Answer: It can be seen in Table 24-9 of https://www.espressif.com.cn/sites/defa ... ual_en.pdf

The CS high time between each segmented transfer is controlled by the value in SPI_CONF_BITLEN control. Some SPI slave has timing constraint in CS high time, for example flash, PSRAM.

If an SPI slave has no timing constraint in CS high time, the value of SPI_CONF_BITLEN can be 0



Q9. Is there a way to explicitly set (bitbang) the state of the MOSI and SCLK (presumably CS# is triival) during the IDLE phase?

Answer: In IDLE phase, the value of MOSI line is the value of SPI_D_POL, the value of SCLK is the value of SPI_CK_IDLE_EDGE.

Thank you for your information, this is really helpful.

For Q8 you are referring to "Table 24-9", but tables in the document are numbered sequentially without chapter numbers and thus there is no table with that number. However, I presume you mean Figure 24-9. If I'm reading Figure 24-9 correctly, and based on your answer, it sounds like half each of SPI_CONF_BITLEN is added to SPI_CS_SETUP_TIME and SPI_CS_HOLD_TIME respectively when moving from one transaction to another, but not the first nor the last transaction?