ESP32-S3 LCD and I2S FULL documentation

ESP_Sprite
Posts: 9985
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby ESP_Sprite » Tue Feb 11, 2025 7:22 am

Baldhead wrote:
Mon Feb 10, 2025 7:38 pm
Hi @ESP_Sprite,

What alignment setting for transfer in gdma should I use in psram ?
MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA should work
Another thing, I must use the function

Code: Select all

Cache_WriteBack_Addr( (uint32_t)p_buffer_a, length );
or the function

Code: Select all

esp_cache_msync( (void*)p_buffer_a, length, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_UNALIGNED );
Ideally esp_cache_msync, that is a 'more official' way to handle this; iirc Cache_WriteBack_Addr works as well but is a ROM function that may change in other ESP32 chips.

Baldhead
Posts: 489
Joined: Sun Mar 31, 2019 5:16 am
Location: Brazil

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Tue Feb 11, 2025 2:06 pm

ESP_Sprite wrote:
Tue Feb 11, 2025 7:22 am
Baldhead wrote:
Mon Feb 10, 2025 7:38 pm
Hi @ESP_Sprite,

What alignment setting for transfer in gdma should I use in psram ?
MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA should work
Another thing, I must use the function

Code: Select all

Cache_WriteBack_Addr( (uint32_t)p_buffer_a, length );
or the function

Code: Select all

esp_cache_msync( (void*)p_buffer_a, length, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_UNALIGNED );
Ideally esp_cache_msync, that is a 'more official' way to handle this; iirc Cache_WriteBack_Addr works as well but is a ROM function that may change in other ESP32 chips.
Alignment i mean the address of returning memory from heap_caps_aligned_alloc(), ie, first parameter of this function.

It need to be 1, 2, 4 .... to gdma(edma) access external psram memory ?

ESP_Sprite
Posts: 9985
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby ESP_Sprite » Wed Feb 12, 2025 12:08 am

Baldhead wrote:
Tue Feb 11, 2025 2:06 pm

Alignment i mean the address of returning memory from heap_caps_aligned_alloc(), ie, first parameter of this function.

It need to be 1, 2, 4 .... to gdma(edma) access external psram memory ?
Ah, I didn't see you were using that. You don't need to; in recent ESP-IDF versions heap_caps_malloc and friends will already align to the correct size if you pass it MALLOC_CAPS_SPIRAM|MALLOC_CAPS_DMA. (I think heap_caps_aligned_alloc also does that so your code should be working anyway.)

Baldhead
Posts: 489
Joined: Sun Mar 31, 2019 5:16 am
Location: Brazil

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Tue Feb 25, 2025 9:36 pm

Hi @ESP_Sprite,

Error:
MSPI Timing: The flash model has not been verified support this feature, please contact espressif business support
cpu_start: init function 0x40380244 has failed (0x106), aborting

I enabled "Adjust PSRAM timing tuning point via on-chip temperature sensor in real-time", image in annex, i think this is the problem, but I think that it should work in this module ( S3-WROOM-2-N32R8V ).

Code: Select all

W (1015) i2c: This driver is an old driver, please migrate your application code to adapt `driver/i2c_master.h`
I (1026) sleep_gpio: Configure to isolate all GPIO pins in sleep state
I (1033) sleep_gpio: Enable automatic switching of GPIO sleep configuration
E (1041) MSPI Timing: The flash model has not been verified support this feature, please contact espressif business support
E (1052) cpu_start: init function 0x40380244 has failed (0x106), aborting
--- 0x40380244: __esp_system_init_fn_psram_adjust_timing_point_via_temperature at C:/esp-idf/components/esp_hw_support/mspi_timing_by_mspi_delay.c:882


abort() was called at PC 0x42003290 on core 0
--- 0x42003290: do_system_init_fn at C:/esp-idf/components/esp_system/startup.c:135



Backtrace: 0x4037a1d5:0x3fceb190 0x40383da9:0x3fceb1b0 0x4038c69a:0x3fceb1d0 0x42003290:0x3fceb240 0x420032c9:0x3fceb270 0x40379cd9:0x3fceb2a0 0x403ccca9:0x3fceb320 0x403cd119:0x3fceb370 0x403c8a31:0x3fceb4b0 0x40045c01:0x3fceb570 0x40043ab6:0x3fceb6f0 0x40034c45:0x3fceb710
--- 0x4037a1d5: panic_abort at C:/esp-idf/components/esp_system/panic.c:454
0x40383da9: esp_system_abort at C:/esp-idf/components/esp_system/port/esp_system_chip.c:92
0x4038c69a: abort at C:/esp-idf/components/newlib/abort.c:38
0x42003290: do_system_init_fn at C:/esp-idf/components/esp_system/startup.c:135
0x420032c9: do_secondary_init at C:/esp-idf/components/esp_system/startup.c:184
 (inlined by) start_cpu0_default at C:/esp-idf/components/esp_system/startup.c:210
0x40379cd9: call_start_cpu0 at C:/esp-idf/components/esp_system/port/cpu_start.c:840 (discriminator 1)





ELF file SHA256: d229c243431a52a7

CPU halted.
Attachments
spiram_clock_temperature_config.jpg
spiram_clock_temperature_config.jpg (24.85 KiB) Viewed 3064 times

Baldhead
Posts: 489
Joined: Sun Mar 31, 2019 5:16 am
Location: Brazil

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Wed Mar 05, 2025 11:16 pm

Baldhead wrote:
Fri Dec 20, 2024 11:00 pm
Hi @Espressif team,

When i change only this bit in my LCD drive, the lcd stops working.

LCD_CAM.lcd_user.lcd_8bits_order = 0;
to
LCD_CAM.lcd_user.lcd_8bits_order = 1;

/** lcd_8bits_order : R/W; bitpos: [19]; default: 0;
* 1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap.
*/

I am using "External SPIRAM" (stay internal to the esp32-s3 chip package).

I believe that this bit only inverts the bytes in the data phase and not in the command phase, right ?

Some suggestion ?

Thank's.
Solved, the problem was very simple.

I send the commands and parameters to the lcd in dma mode too, so, the instruction "LCD_CAM.lcd_user.lcd_8bits_order = 1" was inverting the bytes of parameters too.

I didnt see it in an oscilloscope, but, almost certain that was the problem.

So, when sending lcd commands + parameters i use "LCD_CAM.lcd_user.lcd_8bits_order = 0", and when sending pixels, i use "LCD_CAM.lcd_user.lcd_8bits_order = 1".

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