Can't get interrupt from GPIO pin

[Simon Wright]

I'm working on a bare-metal code for the ESP32-H2, and I can't get an interrupt from a GPIO pin. If this is the wrong place to raise this, I'm sorry - where should I raise it?

Using the Technical Reference Manual Pre-release v0.4. (0.5 doesn't have any updates in sections 1, 6, 9)

Enabling the interrupt

Following TRM 1.6.3.2,

(0) Allocate a so-far-unused machine interrupt (1).

(1) Save the state of MIE and clear it.

(2) I'm going to use edge interrupts, so I set bit 1 in INTPRI_CORE0_CPU_INT_TYPE_REG. (By the way, doesn't this mean that all interrupts from GPIO have to have the same edge/level setting? and is edge/level here the same as edge/level for GPIO pins?)

(3) Set the priority in INTPRI_CORE0_CPU_INT_PRI_1_REG to 15.

(4) Set bit 1 of INTPRI_CORE0_CPU_INT_ENABLE_REG.

(4A) (not in TRM 1.6.3.2; in 9.5.3.1) Set the machine interrupt, 1, in INTMTX_CORE0_GPIO_INTR_MAP_REG.

(5) fence.

(6) Set the new machine interrupt bit (1) in the saved MIE, and restore it to MIE.

Configuring GPIO_3

(1) Configure GPIO_3 to function 1; set IO_MUX_GPIO3_MCU_SEL to 1. (This didn't seem to make any difference).

(2) Disable output by setting bit 3 in GPIO_ENABLE_W1TC_REG (is this right? using W1TS made no difference).

(3) Enable input by setting IO_MUX_GPIO3_FUN_IE to 1.

(4) Enable pull-up by setting IO_MUX_GPIO3_FUN_WPU to 1 and IO_MUX_GPIO3_FUN_WPD to 0.

(5) Set trigger type to any edge by setting GPIO_PIN3_INT_TYPE to 3.

(6) Enable interrupts by setting GPIO_PIN3_INT_ENA to 1 (ordinary interrupt).

Usage

Connecting GPIO_1 to ground doesn't generate an interrupt (but GPIO_IN_REG[3] goes to 0).

[ESP_Lvxinyue]

Hi,

I have forwarded your questions to our support team. I will get back to you once I receive a reply.

I believe there's a typo at the end with GPIO_1. Did you mean GPIO_3?

[ESP_Sprite]

Also, could you possibly share your code? Could be something is wrong in your implementation.

[Simon Wright]

Apologies for late reply: I was on leave.

You're quite right about my referencing GPIO_1 at the end; I meant GPIO_3.

I will point you to my code, but it's in Ada, so may not help much.

Setting up interrupts: https://github.com/simonjwright/FreeRTO ... iemiha.adb (note, at line 154 I've only dealt with GPIO, will address the others after I've got this one working).

Setting up GPIO & enabling interrupt: https://github.com/simonjwright/esp32h2 ... l-gpio.adb

[Simon Wright]

In TRM 1.6.3.2(1), it says "save the state of MIE and clear MIE to 0". I had assumed that it meant the MIE CSR, but maybe it meant the MIE bit in MSTATUS?

I’ve tried this, but it made no difference.

I did notice that when I began the procedure, MSTATUS had both MIE and MPIE set, which is I think contrary to TRM 1.6.2.
It says

Upon execution of MRET/URET instruction, the CPU [...] copies the state of MPIE/UPIE back into MIE/UIE, and subsequently clears MPIE/UPIE. This means that if previously MPIE/UPIE was set, then, after MRET/URET, MIE/UIE will be set, thereby enabling interrupts globally.

. On the other hand, the only interrupt enabled was the timer (7), and it probably hadn’t run yet.

[ESP_Lvxinyue]

Hi,

Please consider if the GPIO interrupt source has been successfully assigned to the CPU interrupt. Try the debugging method:

• Read GPIO_STATUS_REG (0×0044) to check if GPIO interrupt is generated.

• Set INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (0×001C) to 1, then set INTPRI_CPU_INTR_FROM_CPU_0_REG (0×0090) to 1, to check if CPU interrupt configuration is correct. You can also try another CPU interrupt number.

Let me know if it helps. Thanks.