请问ESP-AT是否支持openocd+jtag调试

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xsrlfc
Posts: 5
Joined: Wed Oct 13, 2021 9:10 am

请问ESP-AT是否支持openocd+jtag调试

Postby xsrlfc » Mon Dec 27, 2021 6:42 am

请问目前的esp-at工程是否支持通过指南中openocd+jtag的方法进行调试?

按指南中的方法尝试调试esp-at工程,openocd出现以下错误:

Code: Select all

E:\esp\esp-at>openocd -f /interface/jlink.cfg -f /target/esp32.cfg
Open On-Chip Debugger  v0.10.0-esp32-20200709 (2020-07-09-08:54)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
adapter speed: 12000 kHz
Info : Configured 2 cores
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : J-Link ARM V8 compiled Nov 28 2014 13:44:46
Info : Hardware version: 8.00
Info : VTarget = 5.137 V
Info : clock speed 12000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : Target halted. CPU0: PC=0x400D4D6C (active)
Info : Target halted. CPU1: PC=0x400D4438
Info : Listening on port 3333 for gdb connections
Info : accepting 'gdb' connection on tcp/3333
Error: No symbols for FreeRTOS
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Info : Flash mapping 0: 0x100020 -> 0x3f400020, 76 KB
Info : Flash mapping 1: 0x120020 -> 0x400d0020, 296 KB
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Info : Auto-detected flash bank 'esp32.flash' size 4096 KB
Info : Using flash bank 'esp32.flash' size 4096 KB
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Info : Flash mapping 0: 0x100020 -> 0x3f400020, 76 KB
Info : Flash mapping 1: 0x120020 -> 0x400d0020, 296 KB
Info : Using flash bank 'esp32.irom' size 300 KB
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Info : Flash mapping 0: 0x100020 -> 0x3f400020, 76 KB
Info : Flash mapping 1: 0x120020 -> 0x400d0020, 296 KB
Info : Using flash bank 'esp32.drom' size 80 KB
Error: FreeRTOS: uxTopUsedPriority is not defined, consult the OpenOCD manual for a work-around
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : cpu0: Debug controller 0 was reset.
Info : cpu0: Core 0 was reset.
Info : cpu0: Target halted, PC=0x500000CF, debug_reason=00000000
Info : esp32: Core 0 was reset.
Info : esp32: Debug controller 1 was reset.
Info : esp32: Core 1 was reset.
Info : Target halted. CPU0: PC=0x40000400 (active)
Info : Target halted. CPU1: PC=0x40000400
Info : Target halted. CPU0: PC=0x400D4D6C (active)
Info : Target halted. CPU1: PC=0x400D4488
Error: FreeRTOS: uxTopUsedPriority is not defined, consult the OpenOCD manual for a work-around
GDB无法正常调试:

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E:\esp\esp-at>xtensa-esp32-elf-gdb -x gdbinit build/esp-at.elf
GNU gdb (crosstool-NG esp-2020r3) 8.1.0.20180627-git
Copyright (C) 2018 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=x86_64-host_w64-mingw32 --target=xtensa-esp32-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from build/esp-at.elf...done.
app_main () at ../main/app_main.c:104
warning: Source file is more recent than executable.
104          * Here, disable RWDT to avoid the second restart (RTCWDT_RTC_RESET).
JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
cpu0: Debug controller 0 was reset.
cpu0: Core 0 was reset.
cpu0: Target halted, PC=0x500000CF, debug_reason=00000000
esp32: Core 0 was reset.
esp32: Debug controller 1 was reset.
esp32: Core 1 was reset.
Target halted. CPU0: PC=0x40000400 (active)
Target halted. CPU1: PC=0x40000400
Hardware assisted breakpoint 1 at 0x400d4d6c: file ../main/app_main.c, line 104.
Target halted. CPU0: PC=0x400D4D6C (active)
Target halted. CPU1: PC=0x400D4488
[Switching to Thread 1073459804]
(gdb) l
99           * If esp32 upgraded from v1.1.3.0 to v2.2.0.0+, after the upgraded done,
100          * then each call the esp_restart() will trigger the restart twice.
101          * The first is normal SW_CPU_RESET, the second is extra RTCWDT_RTC_RESET.
102          * (it could happen if upgraded from an old firmware to the new firmware)
103          *
104          * Here, disable RWDT to avoid the second restart (RTCWDT_RTC_RESET).
105          */
106         at_disable_rtc_wdt();
107     #endif
108
(gdb) c
Cannot execute this command without a live selected thread.
(gdb)
在网上搜索发现在新版本的FreeRTOS中似乎已经重新引入了uxTopUsedPriority,但是esp-at目前还是报错,请问现在支持通过这种方法调试吗?

xsrlfc
Posts: 5
Joined: Wed Oct 13, 2021 9:10 am

Re: 请问ESP-AT是否支持openocd+jtag调试

Postby xsrlfc » Mon Dec 27, 2021 9:16 am

发现是esp-at项目的sdkconfig中缺少了CONFIG_ESP32_DEBUG_OCDAWARE=y这个设置,添加后重新编译工程可正常调试。

但是不知道为什么sdkconfig中少了这个配置

ESP_Alson
Posts: 106
Joined: Mon Mar 22, 2021 3:37 am

Re: 请问ESP-AT是否支持openocd+jtag调试

Postby ESP_Alson » Thu Dec 30, 2021 2:33 am

这个选项默认在 ESP-AT 中是不 enable, 如果要开启这个选项,可以在 menuconfig --> Component config --> ESP32-specific 中 enable Make exception and panic handlers JTAG/OCD aware 这个选项。

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