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调用esp_light_sleep_start后，触发TG1WDT_SYS_RST自动重开

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调用esp_light_sleep_start后，触发TG1WDT_SYS_RST自动重开

Posted: Fri Nov 10, 2023 3:52 am
by stevenul
环境: esp-idf-v5.0.3
问题描述 : 调用esp_light_sleep_start后，有机率自动重开，请问这会是什么问题
使用情境 : 项目产品有以下需求，进入休眠，定时唤醒执行业务逻，执行完成后，再进进入轻度睡眠。
init

Code: Select all

    // *EXT0
    printf("Enabling EXT0 wakeup on pin GPIO%d\n", EXT_WAKEUP_PIN);
    ESP_ERROR_CHECK(esp_sleep_enable_ext0_wakeup(EXT_WAKEUP_PIN, INPUT_LEVEL_LOW));
    ESP_ERROR_CHECK(rtc_gpio_pullup_dis(EXT_WAKEUP_PIN));
    ESP_ERROR_CHECK(rtc_gpio_pulldown_en(EXT_WAKEUP_PIN));
    // *timer
    printf("Enabling timer wakeup on 600S\n");
    ESP_ERROR_CHECK(esp_sleep_enable_timer_wakeup(10*1000*1000));
    // *UART
    printf("Enabling UART wakeup on pin GPIO %d\n", SLEEP_MODE_PIN);
    gpio_sleep_set_direction(SLEEP_MODE_PIN, GPIO_MODE_INPUT);
    gpio_sleep_set_pull_mode(SLEEP_MODE_PIN, GPIO_PULLUP_ONLY);

    ESP_ERROR_CHECK(uart_set_wakeup_threshold(SLEEP_MODE_PORT, 3));   
    ESP_ERROR_CHECK(esp_sleep_enable_uart_wakeup(SLEEP_MODE_PORT));
esp_light_sleep_start

Code: Select all

void sleep_mode_task(void* arg){
.
.
.
    while(1){
    .
    .
    .
        ESP_ERROR_CHECK( esp_light_sleep_start());
        switch (esp_sleep_get_wakeup_cause())
                {
                    case ESP_SLEEP_WAKEUP_EXT0: {
                        result = 2;
                        ESP_LOGW("check_wake_up_task","Wake up from ext0");
                            break;
                        }
                    case ESP_SLEEP_WAKEUP_UART:{
                        result = 8 ;
                        ESP_LOGW("check_wake_up_task","Wake up from uart");
                        break;
                    }
                    case ESP_SLEEP_WAKEUP_TIMER: {
                        result = 4 ;
                        ESP_LOGW("check_wake_up_task","Wake up from timer");
                        break;
                    }
                    default:
                        ESP_LOGE("check_wake_up_task","Wake up no value");
                        break;
                }[Codebox=c file=Untitled.c][/Codebox]
	.
	.
	.
    }
}
调用esp_light_sleep_start后，有机率自动重开

Code: Select all

D ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x8 (TG1WDT_SYS_RST),boot:0xa (SPI_FAST_FLASH_BOOT)
Saved PC:0x40382a1d
0x40382a1d: _xt_context_save at C:/Espressif/frameworks/esp-idf-v5.0.3/components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_context.S:157

SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce3810,len:0x468
load:0x403c9700,len:0xad4
load:0x403cc700,len:0x2808
entry 0x403c9880
完整log

Code: Select all

D ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x8 (TG1WDT_SYS_RST),boot:0xa (SPI_FAST_FLASH_BOOT)
Saved PC:0x403829e6
0x403829e6: _xt_context_save at C:/Espressif/frameworks/esp-idf-v5.0.3/components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_context.S:112

SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce3810,len:0x468
load:0x403c9700,len:0xad4
load:0x403cc700,len:0x2808
entry 0x403c9880
I (290) cpu_start: Multicore app
I (290) octal_psram: vendor id    : 0x0d (AP)
I (290) octal_psram: dev id       : 0x02 (generation 3)
I (293) octal_psram: density      : 0x03 (64 Mbit)
I (299) octal_psram: good-die     : 0x01 (Pass)
I (304) octal_psram: Latency      : 0x01 (Fixed)
I (309) octal_psram: VCC          : 0x01 (3V)
I (314) octal_psram: SRF          : 0x01 (Fast Refresh)
I (320) octal_psram: BurstType    : 0x01 (Hybrid Wrap)
I (326) octal_psram: BurstLen     : 0x01 (32 Byte)
I (332) octal_psram: Readlatency  : 0x02 (10 cycles@Fixed)
I (338) octal_psram: DriveStrength: 0x00 (1/1)
D (343) MSPI Timing: tuning success, best point is index 5
I (348) MSPI Timing: PSRAM timing tuning index: 5
I (354) esp_psram: Found 8MB PSRAM device
I (358) esp_psram: Speed: 80MHz
V mmu_psram: Instructions from flash page19 copy to SPIRAM page0, Offset: 19
V (407) mmu_psram: after copy instruction, page_id is 7
I (408) mmu_psram: Instructions copied and mapped to SPIRAM
V (408) esp_psram: after copy .text, used page is 7, start_page is 7, psram_available_size is 7929856 B
V mmu_psram: Rodata from flash page1 copy to SPIRAM page7, Offset: -6
V (511) mmu_psram: after copy rodata, page_id is 25
I (511) mmu_psram: Read only data copied and mapped to SPIRAM
V (511) esp_psram: after copy .rodata, used page is 18, start_page is 25, psram_available_size is 6750208 B
V (521) mmu: after coalescing, 1 regions are left
V (526) mmu: found laddr is 0x190000
V (529) esp_psram: 8bit-aligned-region: actual_mapped_len is 0x670000 bytes
V (536) esp_psram: 8bit-aligned-range: 0x670000 B, starting from: 0x3c190000
I (544) cpu_start: Pro cpu up.
I (547) cpu_start: Starting app cpu, entry point is 0x403797e0
0x403797e0: call_start_cpu1 at C:/Espressif/frameworks/esp-idf-v5.0.3/components/esp_system/port/cpu_start.c:143     

I (0) cpu_start: App cpu up.
V CACHE_ERR: illegal error intr clr & ena mask is: 0x3f
V CACHE_ERR: core 1 access error intr clr & ena mask is: 0x1f
I (918) esp_psram: SPI SRAM memory test OK
D (918) efuse: In EFUSE_BLK1__DATA4_REG is used 7 bits starting with 20 bit
D (918) efuse: In EFUSE_BLK1__DATA5_REG is used 8 bits starting with 3 bit
D (925) efuse: In EFUSE_BLK1__DATA5_REG is used 5 bits starting with 11 bit
D (932) efuse: In EFUSE_BLK1__DATA4_REG is used 7 bits starting with 13 bit
D (939) efuse: In EFUSE_BLK1__DATA4_REG is used 7 bits starting with 20 bit
D (946) efuse: In EFUSE_BLK1__DATA4_REG is used 5 bits starting with 27 bit
D (953) efuse: In EFUSE_BLK1__DATA5_REG is used 3 bits starting with 0 bit
D (960) efuse: In EFUSE_BLK1__DATA5_REG is used 8 bits starting with 3 bit
D (967) efuse: In EFUSE_BLK1__DATA4_REG is used 7 bits starting with 13 bit
D (974) efuse: In EFUSE_BLK1__DATA4_REG is used 7 bits starting with 20 bit
D (981) efuse: In EFUSE_BLK1__DATA4_REG is used 5 bits starting with 27 bit
D (988) efuse: In EFUSE_BLK1__DATA5_REG is used 3 bits starting with 0 bit
D (995) efuse: In EFUSE_BLK1__DATA5_REG is used 8 bits starting with 3 bit
D (1010) clk: RTC_SLOW_CLK calibration value: 3873434
V CACHE_ERR: illegal error intr clr & ena mask is: 0x3f
V CACHE_ERR: core 0 access error intr clr & ena mask is: 0x1f
I (1019) cpu_start: Pro cpu start user code
I (1023) cpu_start: cpu freq: 240000000 Hz
I (1027) cpu_start: Application information:
I (1032) cpu_start: Project name:     hello_world
I (1038) cpu_start: App version:      1
I (1042) cpu_start: Compile time:     Nov 10 2023 10:08:02
I (1048) cpu_start: ELF file SHA256:  a93a6b13b2eab2d7...
I (1054) cpu_start: ESP-IDF:          v5.0.3-dirty
I (1060) cpu_start: Min chip rev:     v0.0
I (1065) cpu_start: Max chip rev:     v0.99 
I (1070) cpu_start: Chip rev:         v0.2
V (1074) memory_layout: reserved range is 0x3c180d74 - 0x3c180d94
D (1081) memory_layout: Checking 5 reserved memory ranges:
D (1086) memory_layout: Reserved memory range 0x3c000000 - 0x3e000000
D (1093) memory_layout: Reserved memory range 0x3fc88000 - 0x3fc9b700
D (1099) memory_layout: Reserved memory range 0x3fc9b700 - 0x3fcaa738
D (1106) memory_layout: Reserved memory range 0x3fceee34 - 0x3fcf0000
D (1112) memory_layout: Reserved memory range 0x600fe000 - 0x600fe034
D (1119) memory_layout: Building list of available memory regions:
V (1125) memory_layout: Examining memory region 0x3c000000 - 0x3e000000
V (1132) memory_layout: Region 0x3c000000 - 0x3e000000 inside of reserved 0x3c000000 - 0x3e000000
V (1141) memory_layout: Examining memory region 0x3fc88000 - 0x3fc90000
V (1147) memory_layout: Region 0x3fc88000 - 0x3fc90000 inside of reserved 0x3fc88000 - 0x3fc9b700
V (1156) memory_layout: Examining memory region 0x3fc90000 - 0x3fca0000
V (1163) memory_layout: Start of region 0x3fc90000 - 0x3fca0000 overlaps reserved 0x3fc88000 - 0x3fc9b700
V (1173) memory_layout: Region 0x3fc9b700 - 0x3fca0000 inside of reserved 0x3fc9b700 - 0x3fcaa738
V (1181) memory_layout: Examining memory region 0x3fca0000 - 0x3fcb0000
V (1188) memory_layout: Start of region 0x3fca0000 - 0x3fcb0000 overlaps reserved 0x3fc9b700 - 0x3fcaa738
D (1198) memory_layout: Available memory region 0x3fcaa738 - 0x3fcb0000
V (1204) memory_layout: Examining memory region 0x3fcb0000 - 0x3fcc0000
D (1211) memory_layout: Available memory region 0x3fcb0000 - 0x3fcc0000
V (1218) memory_layout: Examining memory region 0x3fcc0000 - 0x3fcd0000
D (1225) memory_layout: Available memory region 0x3fcc0000 - 0x3fcd0000
V (1231) memory_layout: Examining memory region 0x3fcd0000 - 0x3fce0000
D (1238) memory_layout: Available memory region 0x3fcd0000 - 0x3fce0000
V (1245) memory_layout: Examining memory region 0x3fce0000 - 0x3fce9710
D (1251) memory_layout: Available memory region 0x3fce0000 - 0x3fce9710
V (1258) memory_layout: Examining memory region 0x3fce9710 - 0x3fcf0000
V (1265) memory_layout: End of region 0x3fce9710 - 0x3fcf0000 overlaps reserved 0x3fceee34 - 0x3fcf0000
D (1274) memory_layout: Available memory region 0x3fce9710 - 0x3fceee34
V (1281) memory_layout: Examining memory region 0x600fe000 - 0x60100000
V (1287) memory_layout: Start of region 0x600fe000 - 0x60100000 overlaps reserved 0x600fe000 - 0x600fe034
D (1297) memory_layout: Available memory region 0x600fe034 - 0x60100000
I (1304) heap_init: Initializing. RAM available for dynamic allocation:
D (1311) heap_init: New heap initialised at 0x3fcaa738
I (1316) heap_init: At 3FCAA738 len 0003EFD8 (251 KiB): DRAM
I (1323) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DRAM
D (1329) heap_init: New heap initialised at 0x600fe034
I (1335) heap_init: At 600FE034 len 00001FCC (7 KiB): RTCRAM
I (1341) esp_psram: Adding pool of 6592K of PSRAM memory to heap allocator
V (1348) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (1355) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0x40E
D (1363) intr_alloc: Connected src 39 to int 2 (cpu 0)
V (1369) memspi: raw_chip_id: 18405E

V (1372) memspi: chip_id: 5E4018

V (1376) memspi: raw_chip_id: 18405E

V (1379) memspi: chip_id: 5E4018

D (1383) spi_flash: trying chip: issi
D (1387) spi_flash: trying chip: gd
D (1390) spi_flash: trying chip: mxic
D (1394) spi_flash: trying chip: winbond
D (1398) spi_flash: trying chip: boya
D (1402) spi_flash: trying chip: th
D (1405) spi_flash: trying chip: mxic (opi)
D (1410) spi_flash: trying chip: generic
I (1414) spi_flash: detected chip: generic
I (1418) spi_flash: flash io: qio
D (1422) chip_generic: set_io_mode: status before 0x200
V (1428) chip_generic: set_io_mode: status update 0x200
D (1433) cpu_start: calling init function: 0x420473ec
0x420473ec: _GLOBAL__sub_I__ZN9__gnu_cxx9__freeresEv at eh_alloc.cc:?

D (1438) cpu_start: calling init function: 0x420473b0
0x420473b0: _GLOBAL__sub_I___cxa_get_globals_fast at eh_globals.cc:?

D (1443) cpu_start: calling init function: 0x420431e4
0x420431e4: esp_ipc_init at C:/Espressif/frameworks/esp-idf-v5.0.3/components/esp_system/esp_ipc.c:115

D (1448) cpu_start: calling init function: 0x42002c6c
0x42002c6c: esp_reset_reason_init at C:/Espressif/frameworks/esp-idf-v5.0.3/components/esp_system/port/soc/esp32s3/reset_reason.c:67

D (1453) cpu_start: calling init function: 0x42001d48
0x42001d48: esp_init_app_elf_sha256 at C:/Espressif/frameworks/esp-idf-v5.0.3/components/esp_app_format/esp_app_desc.c:69

D (1459) cpu_start: calling init function: 0x42006cc8 on core: 0
0x42006cc8: __esp_system_init_fn_esp_timer_startup_init at C:/Espressif/frameworks/esp-idf-v5.0.3/components/esp_timer/src/esp_timer.c:551

V (1465) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (1471) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0xC02
D (1479) intr_alloc: Connected src 59 to int 3 (cpu 0)
D (1484) cpu_start: calling init function: 0x420451bc on core: 0
0x420451bc: __esp_system_init_fn_esp_sleep_startup_init at C:/Espressif/frameworks/esp-idf-v5.0.3/components/esp_hw_support/sleep_modes.c:1516

I (1491) sleep: Configure to isolate all GPIO pins in sleep state
I (1497) sleep: Enable automatic switching of GPIO sleep configuration
D (1504) cpu_start: calling init function: 0x4200296c on core: 0
0x4200296c: __esp_system_init_fn_init_components0 at C:/Espressif/frameworks/esp-idf-v5.0.3/components/esp_system/startup.c:484

V (1522) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (1522) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0x40E
D (1525) intr_alloc: Connected src 79 to int 9 (cpu 0)
I (1531) cpu_start: Starting scheduler on PRO CPU.
V (1536) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (1536) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0x402
D (1536) intr_alloc: Connected src 57 to int 12 (cpu 0)
V (1536) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): checking args
V (1546) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0x40E
D (1546) intr_alloc: Connected src 80 to int 2 (cpu 1)
I (1556) cpu_start: Starting scheduler on APP CPU.
V (1566) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): checking args
V (1566) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0x402
D (1576) intr_alloc: Connected src 58 to int 3 (cpu 1)
D (1586) heap_init: New heap initialised at 0x3fce9710
I (1586) esp_psram: Reserving pool of 32K of internal memory for DMA/internal allocations
D (1596) esp_psram: Allocating block of size 32768 bytes
V (1596) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (1606) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0xE
D (1616) intr_alloc: Connected src 52 to int 13 (cpu 0)
Hello world!

Re: 调用esp_light_sleep_start后，触发TG1WDT_SYS_RST自动重开

Posted: Thu Nov 16, 2023 6:01 am
by stevenul
我发现问题可能与萤幕方面有关，当我不配置萤幕相关的任务时，不会有这个问题。但如果我配置了，并且在进入睡眠模式之前把她挂起，仍然会有TG1WDT_SYS_RST自动重启的问题。只有当完全不配置时，才不会有问题。请问我该如何修改这个问题呢?

专案代码已上传
https://github.com/stevenlu0975/ESP32_sleep_issue
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