I2S clocks are inaccurate

[Alex6666]

I am trying to use direct audio connection between device with ESP32-S3R8 and voice codec and host with modem (located in the host). Sample rate is 8K. I faced to inaccurate I2S clocks on codec side (ESP32 generates clocks for codec). I measured the clocks with oscilloscope which can measure frequency and it shows MCLK 4.103 MHz and WS 8.013 KHz instead of expected 4.096 MHz and 8 KHz respectively. And it is average frequency so possible jitter already taken into account here.

bip_mclk.png (240.63 KiB) Viewed 4050 times

bip.png (97.66 KiB) Viewed 4050 times

Also I measured time of getting of 80 samples of microphone data (expected time is 10 ms) in ESP32 by function esp_timer_get_time().
List of measured time:

1120933: ELAPSED: 9983
1120943: ELAPSED: 9983
1120953: ELAPSED: 9983
1120963: ELAPSED: 9983
1120973: ELAPSED: 9983
1120983: ELAPSED: 9983
1120993: ELAPSED: 9983
1121003: ELAPSED: 9983
1121013: ELAPSED: 9988
1121023: ELAPSED: 9984
1121033: ELAPSED: 9984
1121043: ELAPSED: 9984
1121053: ELAPSED: 9984
1121062: ELAPSED: 9979
1121072: ELAPSED: 9983
1121082: ELAPSED: 9983
1121092: ELAPSED: 9983
1121102: ELAPSED: 9983
1121112: ELAPSED: 9983
1121122: ELAPSED: 9983
1121132: ELAPSED: 9983
1121142: ELAPSED: 9983
1121152: ELAPSED: 9983
1121162: ELAPSED: 9983

The average time of getting data is 9983 microseconds. If we get frequency of clocks measured by oscilloscope we will get 80 * 1 / 8013 * 10^6 = 9983.776 microseconds and it corresponds with time measured by microcontoller.

Also I have measured I2S WS clocks on modem side (in the host) by oscilloscope and by microcontroller. Clocks are generated by modem.

beg.png (88 KiB) Viewed 4050 times

List of measured time:

746425: ELAPSED: 10001
746435: ELAPSED: 9998
746445: ELAPSED: 9999
746455: ELAPSED: 10000
746465: ELAPSED: 9998
746475: ELAPSED: 9999
746485: ELAPSED: 10001
746495: ELAPSED: 9996
746505: ELAPSED: 10000
746515: ELAPSED: 9996
746525: ELAPSED: 9999
746535: ELAPSED: 10000
746545: ELAPSED: 9998
746555: ELAPSED: 10000
746565: ELAPSED: 9998
746575: ELAPSED: 9998
746585: ELAPSED: 10001
746595: ELAPSED: 9996
746605: ELAPSED: 10001
746615: ELAPSED: 9995
746625: ELAPSED: 9999
746635: ELAPSED: 9999
746645: ELAPSED: 10001

The average time of getting data is 10 ms and clocks on modem side measured by the same oscilloscope is 8 KHz as expected.

Also I have added trace of I2S registers which are responsible for MCLK generation. Below is output:

TX_I2S: x 15, y 0, z 1, y1 0
RX_I2S: x 15, y 0, z 1, y1 0

Values of registers are correct and corresponds to divider 39.0625 to generate 4.096 MHz from 160 MHz PLL clock. But if we apply divider 39 to PLL clock we will get 4102564.1 Hz for MCLK clock and 8 012.82 Hz for WS clock and it corresponds to what I have measured by oscilloscope and microcontroller. It looks like fractional part of divider is not applied to PLL clock in I2S clock generation.
Used ESP-IDF commit: cbce221e88d52665523093b2b6dd0ebe3f1243f1 (tag v5.1)

[CCER_CCER]

Hi Alex6666 ，
This is indeed an issue on v5.1. But on release/v5.1 you will get 8KHz LRCK frequency, you can try it, hope this will solve your problem.
Please let me know if there is any progress.

[Alex6666]

I have tried changes of I2S from ESP-IDF v5.2 and it's helped! Now MCLK clock as well as WS clock are correct. Thank you!

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3_clk.png (83.91 KiB) Viewed 3312 times