ESP32 Forum

EDITS:
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what we know about - summarized :

a) in this version there is no 5 GHz but it is on the work

b) in this version is USB

c) TinyBASIC port in ROM?
no in this not but there is plan 4 versions of based on the new architecture

d) it is a Tensilica / RISC V are in the pipelines.

e) there are beta user / request possible

f) there is no CAP1 and CAP2 any more


...still in edit work this post ...






Hi folks ...

spotted in the wild :



best wishes
rudi

no guarantee! pure guess

best wishes
rudi

So how many things from "What would you like to see in The Next Chip?" made it inside?

Not quite sure looking at picture - but is the chip size 2x bigger?
More cores? )

Hi WiFive

in advance:
Cause the name Chip7 2-2-A
i think there was a few month ago where few "engineer samples" are tested at espressif
cause here you find a hint :
"/home/cff/gittree/chip7.1_phy/chip_7.1/board_code/app_test/pp/phy/phy_chip_v7_ana.c"

also it can be mean, that we talk about the IP 7 ( RiscV ), 64Bit, 8 core, 5-6 Pipes, Atomic,
Linux compatible and further more
( i think it is a preview thing ( 2..4 core .. but i can image that is a 64 bit.. )

WiFive wrote: ↑

Wed Mar 20, 2019 12:39 pm

So how many things from "What would you like to see in The Next Chip?" made it inside?

i think we are very flexible in this, cause it looks like we can configure each 47 IO 's like we want and need.
I think we get 5 GHz -
i think over the name at the bottom, UO0AN5V280, there are few infos perhabs in this?

U 64 Bit
O ??
0 ??
A Atomic
N Normal Mode no compressed for code density
5 5 stage variable pipeline
V Risc-V
2 Dual Core, Dual Wifi, Dual Wifi & BT/BLE
8 8 Core ?? 8 Mbit eMbeddedFlash ?? 8 MByte eMbeddedFlash ?? .. 8 mm package ??
0 ( No eMbedded Flash ?? )

Deouss wrote: ↑

Wed Mar 20, 2019 1:33 pm

Not quite sure looking at picture - but is the chip size 2x bigger?
More cores? )

we drill and keep looking further

best wishes
rudi

New think over UO0AN5V280

U 64 Bit
O ??
0 ??
A Atomic
N Normal Mode no compressed for code density
5 5 stage variable pipeline ?? 5 Core ( Quad 4xU7 + 1xS7 ) ??
V Risc-V
2 Dual Core, Dual Wifi, Dual Wifi & BT/BLE
8 8 Core ?? 8 Mbit eMbeddedFlash ?? 8 MByte eMbeddedFlash ?? .. 8 mm package ??
0 ( No eMbedded Flash ?? )

best wishes
rudi

Chip 7 = 7nm

Just to temper expectations a bit: this is likely not going to be the top-of-the-line powerhouse that you guys think/hope it will be, as seen in the posts in this topic. Not saying we're not working on one of those but this is not it. (It does have a few picks from the ideas of the 'what would you like to see in the new chip' topic inside, though.)

ESP_Sprite wrote: ↑

Thu Mar 21, 2019 7:22 am

Just to temper expectations a bit: this is likely not going to be the top-of-the-line powerhouse that you guys think/hope it will be, ..

hehe no 8 cores

edit:
would have been too nice -
but I also thought of a "new esp32"
So an improved and expanded.
he was announced
"FYI, there will be a new" ESP32 "next year."
/edit
it would be a tick to small for all the wishes and think on from the "What would you like to see in The Next Chip?" thread
do you can whisper about the RF filter? looks bodged. 5 GHz ?
can imagine that 5 GHz work here but not sure -
we continue to speculate
the design it self looks like an enlarged scope of esp32-wrover and more much more gpio
best wishes
rudi

07 2019 - June 2019 ?

I think it says UO0AN6V280 - 6 or 8 cores?