SPI flash driver

PeterR
Posts: 621
Joined: Mon Jun 04, 2018 2:47 pm

SPI flash driver

Postby PeterR » Mon Oct 22, 2018 1:35 pm

I have been given the requirement to add data logging onto a SPI flash.
I cannot easily use the master FLASH as I also need to use the PSRAM.

The ESP32 spi flash library is only intended for use with the master (the program) FLASH.
I thought that a little cut n paste would resolve but the driver disappears under the hood when making use of ROM routines.

Does anyone one know of a decent SPI flash driver available on a permissive license (not GPL)?
I only need simple block access ATM.
& I also believe that IDF CAN should be fixed.

WiFive
Posts: 3529
Joined: Tue Dec 01, 2015 7:35 am

Re: SPI flash driver

Postby WiFive » Mon Oct 22, 2018 8:45 pm


PeterR
Posts: 621
Joined: Mon Jun 04, 2018 2:47 pm

Re: SPI flash driver

Postby PeterR » Tue Oct 23, 2018 10:40 am

Awesome; you even guessed my chip/size! I'll get testing!
& I also believe that IDF CAN should be fixed.

PeterR
Posts: 621
Joined: Mon Jun 04, 2018 2:47 pm

Re: SPI flash driver

Postby PeterR » Fri Nov 02, 2018 1:38 pm

Please note that ExtFlash does not initialise 'is_qpi' & this can give you performance issues or errors depending on what you want!
& I also believe that IDF CAN should be fixed.

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fly135
Posts: 606
Joined: Wed Jan 03, 2018 8:33 pm
Location: Orlando, FL

Re: SPI flash driver

Postby fly135 » Sat Nov 03, 2018 7:04 pm

I cannot easily use the master FLASH as I also need to use the PSRAM.
It seems that WiFive understands your question, but I'm confused. I'm assuming that "master FLASH" is the flash used to hold the application and other things. Why can you not use that flash for data storage? And what does PSRAM have to do with the problem you are having?

John A

PeterR
Posts: 621
Joined: Mon Jun 04, 2018 2:47 pm

Re: SPI flash driver

Postby PeterR » Mon Nov 05, 2018 10:42 am

Hi,
The issue was the lack of a 'is_qpi' initialiser in the downloaded driver.
Gonna try -Weffc++ and start coding properly.

To answer your questions - my understanding is that I must be running from IRAM in order to write main/master FLASH -
' This means that both CPUs must be running code from IRAM and only reading data from DRAM while flash write operations occur.'
From the above I understand that when writing main FLASH; (a) I must be running in IRAM and (b) cannot write to PSRAM
My program is quite large (>> larger than IRAM) and needs to ensure low latency for a number of activities including writing to PSRAM. I expect that FLASH erase/writes will take 10mS or more and so these restrictions seem to make main FLASH use impractical for me.
Perhaps 'cannot' is not strictly true but using main FLASH for logging seems to be a pain.
& I also believe that IDF CAN should be fixed.

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