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Full duplex SPI MODE 3 CS line pulls down at same time of CLK
Posted: Wed Sep 26, 2018 6:27 pm
by dzRBRglobal
When capture signal on my digital analyzer in mode 3, the digital analyzer always complains "CLK idle error". If I set my digital analyzer to mode 0, it can decode the signal. I found the CS pulls down at same time of CLK. Should the CS pull down before CLK?
Re: Full duplex SPI MODE 3 CS line pulls down at same time of CLK
Posted: Wed Sep 26, 2018 7:05 pm
by michprev
Generally CS should be always toggled before CLK signal. There is a hardware bug where setting cs_ena_pretrans does not have any effect in full duplex.
You can control CS line as GPIO (set it low before SPI transmission, set it high after transmission).
Re: Full duplex SPI MODE 3 CS line pulls down at same time of CLK
Posted: Mon Oct 01, 2018 1:24 pm
by dzRBRglobal
Thank you very much for your reply.
So what is the work around for now if I want to use DMA ? define a GPIO and set it in pre call function and reset in post call function?