ESP32 Forum

Posted: **Wed Sep 05, 2018 11:27 pm**

Hello my friends!

I'm excited about learning this ESP32.

I would like to ask your expert opinions on how to get started programming on it to stream audio from my phone (use I2S output from ESP32 to DAC), as well as send data via BLE (I can use SPI, UART or I2C from ESP32 to MCU).

Should I use arduino, or am I better off programming the ESP32 directly? Or is it even possible to do it using AT commands?

Thank you!

Posted: **Tue Sep 11, 2018 10:55 am**

https://github.com/espressif/esp-idf/tr ... gatts_coex

Posted: **Thu Sep 13, 2018 3:03 am**

Awesome, thank you!

Posted: **Sun Sep 16, 2018 6:29 pm**

I've got the demo to work, but my Bit Clock pin is MCLK / 8 (or 32 x FS), which in this case is 1.411 MHz for a 44.1kHz sampling rate.

Is there ANYWAY to make this BCK pin MCLK / 4 (or 64 x FS)?

Thanks again!

Posted: **Sun Sep 16, 2018 10:07 pm**

Hello my friends,

I've been trying very hard here to get this to work, any help is sincerely appreciated!

I'm working with the "a2dp_gatts_coex" example.
I changed the bits per sample to 32, and the sample rate to 48 KHz.
That makes my BCK jump to the correct 64 FS to interface with my DSP via I2S.
So then my clocks are:
MCLK = 12.288Mhz
BCLK = 3.072 Mhz <- 64 FS works fine
LRCLK = 48 KHz

Perfect!

The problem is, as soon as connect the bluetooth, it "automatically" jumps back 44.1 kHz and 16 Bits (BCK = 32 FS), which makes the I2S interface with my DSP crash.
Then my clocks become:
MCLK = 11.289 MHz
BCLK = 1.411 MHz <- I2S interface crashes, DSP does not support 32 FS.
LRCLK = 44.1 KHz.

These are the adjustments I made.
What other adjustments do I need to make?
How about the DMA buffers, do these need increase?

Code: Select all

    i2s_config_t i2s_config = {
#ifdef CONFIG_A2DP_SINK_OUTPUT_INTERNAL_DAC
        .mode = I2S_MODE_DAC_BUILT_IN,
#else
        .mode = I2S_MODE_MASTER | I2S_MODE_TX,                                  // Only TX
#endif
        .sample_rate = 48000, //FP Originally 44100
        .bits_per_sample = 32, //FP originally 16
        .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,                           //2-channels I2S_CHANNEL_FMT_RIGHT_LEFT
        .communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
        .dma_buf_count = 6,
        .dma_buf_len = 60,                                                      //
        .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1                                //Interrupt level 1
    };

Thank you!

Posted: **Mon Sep 17, 2018 2:39 am**

Very well,

On the file "bt_app_av.c" I found this and I added another line to "lock" the i2s clock / bit configuration in place:

Code: Select all

    case ESP_A2D_AUDIO_CFG_EVT: {
        a2d = (esp_a2d_cb_param_t *)(p_param);
        ESP_LOGI(BT_AV_TAG, "A2DP audio stream configuration, codec type %d", a2d->audio_cfg.mcc.type);
        // for now only SBC stream is supported
        if (a2d->audio_cfg.mcc.type == ESP_A2D_MCT_SBC) {
            int sample_rate = 16000;
            char oct0 = a2d->audio_cfg.mcc.cie.sbc[0];
            if (oct0 & (0x01 << 6)) {
                sample_rate = 32000;
            } else if (oct0 & (0x01 << 5)) {
                sample_rate = 44100;
            } else if (oct0 & (0x01 << 4)) {
                sample_rate = 48000;
            }
[b]            //i2s_set_clk(0, sample_rate, 16, 2); //FP Original 
            i2s_set_clk(0, 48000, 32, 2); //FP modifying to see if this would prevent BCLK from rolling back to 32FS[/b]

Now it does not "jump back" to 44.1 16-bits. It stays at 48K 32-bit.

It "works", I can hear the music playing through my DSP, except that the pitch is shifted up by 2x. A 500 signal becomes a 1kHz signal with some pops and clicks.

Is there is a way to put only 16 bits of data on the buffer while having it configured for "32" bits?
Because the ONLY reason it is using 32 bits right now is to simply put BCLK on the correct frequency of 3.072 Mhz.
Please help!

Posted: **Sat Sep 29, 2018 10:24 pm**

I'm happy to say that I found out what the problem was.
My DSP could run just fine with 32FS. The problem is that without use_apll=1 on the i2s config, the clock was unstable and the DSP refused to work. Once use_apll = 1 was set, everything worked.

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