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CLK on SPI master ESP32

Posted: Tue Jul 10, 2018 3:36 pm
by Xarlan
Hello everybody.

I have problem with SPI master on ESP32.

I compile and upload the example of spi-master https://github.com/espressif/esp-idf/tr ... spi_master
and get the follow picture:
DSC_0998.JPG
yellow line - CLK, GPIO19
red line - MOSI, GPIO23.
DSC_0998.JPG (2.78 MiB) Viewed 7174 times
On this picture CLK is fine, and we can see that some data is transfer (red line).

I took this example as a basis:

Code: Select all

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_system.h"
#include "driver/spi_master.h"
#include "soc/gpio_struct.h"
#include "driver/gpio.h"

#define PIN_NUM_MISO 25
#define PIN_NUM_MOSI 23
#define PIN_NUM_CLK  19
#define PIN_NUM_CS   22

void lcd_cmd(spi_device_handle_t spi, const uint8_t cmd)
{
    esp_err_t ret;
    spi_transaction_t t;

    memset(&t, 0, sizeof(t));       //Zero out the transaction

    t.length=8;                     //Command is 8 bits
    t.tx_buffer=&cmd;               //The data is the cmd itself

//    ret=spi_device_transmit(spi, &t);  //Transmit!
    ret=spi_device_queue_trans(spi, &t, portMAX_DELAY);

    assert(ret==ESP_OK);            //Should have had no issues.
}


void app_main()
{
    esp_err_t ret;
    spi_device_handle_t spi;

    spi_bus_config_t 	buscfg;

			buscfg.miso_io_num = PIN_NUM_MISO;
			buscfg.mosi_io_num=PIN_NUM_MOSI;
			buscfg.sclk_io_num=PIN_NUM_CLK;
			buscfg.quadwp_io_num=-1;
			buscfg.quadhd_io_num=-1;

	spi_device_interface_config_t devcfg;

			devcfg.clock_speed_hz=100000;           	  	//Clock out
			devcfg.mode=0;                              //SPI mode 0
			devcfg.spics_io_num=PIN_NUM_CS;             //CS pin
			devcfg.queue_size=7;                        //We want to be able to queue 7 transactions at a time


    ret=spi_bus_initialize(HSPI_HOST, &buscfg, 0);			// Initialize the SPI bus
    printf("spi_bus_init = %d\n", ret);
    ESP_ERROR_CHECK(ret);


    ret=spi_bus_add_device(HSPI_HOST, &devcfg, &spi);		// Attach the MAX3421 to the SPI bus
    printf("spi_bus_add_device = %d\n", ret);
    ESP_ERROR_CHECK(ret);

    while ( 1 )
    {
    	printf("LED On\n");
    	lcd_cmd(spi, 0xA2);
    	vTaskDelay(1000 / portTICK_PERIOD_MS);

    	printf("LED OFF\n");
    	lcd_cmd(spi, 0xA2);
    	vTaskDelay(1000 / portTICK_PERIOD_MS);
    }
}
To transfer data I try use:
"ret=spi_device_transmit(spi, &t); //Transmit!"
or
"ret=spi_device_queue_trans(spi, &t, portMAX_DELAY);"

However, I get very strange signal on CLK line:
spi_02.png
yellow line - CLK, GPIO19
red line - MOSI, GPIO23.
spi_02.png (2.04 MiB) Viewed 7174 times
Also I don't use DMA
ret=spi_bus_initialize(HSPI_HOST, &buscfg, 0); // Initialize the SPI bus
So, the main question - what I do wrong? I can't understand what else needs to be configured that signal on CLK line in SPI master mode will be correct.

Thank you

Re: CLK on SPI master ESP32

Posted: Wed Jul 11, 2018 3:44 am
by ESP_Sprite
Make sure that your buscfg and devcfg are zeroed out first. At the moment, you're getting random crap from the stack in members of those structures that you didn't explicitly fill in.

Re: CLK on SPI master ESP32

Posted: Thu Jul 12, 2018 10:11 am
by Xarlan
Hm... soudns litle bit strange, but after

Code: Select all

    spi_bus_config_t 	buscfg;

    		buscfg.mosi_io_num 		= PIN_NUM_MOSI;
    		buscfg.miso_io_num 		= PIN_NUM_MISO;
			buscfg.sclk_io_num 		= PIN_NUM_CLK;
			buscfg.quadwp_io_num 	= -1;
			buscfg.quadhd_io_num 	= -1;
			buscfg.max_transfer_sz 	= 0;
			buscfg.flags			= SPICOMMON_BUSFLAG_MASTER;

		    ret=spi_bus_initialize(HSPI_HOST, &buscfg, 0);			// Initialize the SPI bus
		    printf("spi_bus_init = %d\n", ret);
		    ESP_ERROR_CHECK(ret);

	spi_device_interface_config_t devcfg;
			devcfg.address_bits		= 0;
			devcfg.command_bits		= 0;
			devcfg.dummy_bits		= 0;
			devcfg.mode				= 0;              //SPI mode 0
			devcfg.duty_cycle_pos	= 0;
			devcfg.cs_ena_posttrans = 0;
			devcfg.cs_ena_pretrans	= 0;
			devcfg.clock_speed_hz	= 100000;           	  	//Clock out
			devcfg.spics_io_num		= PIN_NUM_CS;             //CS pin
			devcfg.flags			= 0;
			devcfg.queue_size		= 1;                        //We want to be able to queue 7 transactions at a time
			devcfg.pre_cb			= NULL;
			devcfg.post_cb			= NULL;

    ret=spi_bus_add_device(HSPI_HOST, &devcfg, &spi);		// Attach the MAX3421 to the SPI bus
    printf("spi_bus_add_device = %d\n", ret);
    ESP_ERROR_CHECK(ret);
I will see correct CLK and MISO data.

Thank you.

Re: CLK on SPI master ESP32

Posted: Sat Jul 14, 2018 3:12 pm
by ESP_Sprite
No, that's not strange at all: because you didn't zero out your variable before setting the members, the flags member got crap in it, causing everything to break. You are still not zeroing out your variable, thus running the risk of your program breaking again. If you copy the SPI master example, please also copy the way this variable is initialized, otherwise your program will break in weird and wonderful ways in the future.