ESP32 Forum

Hi,

I am trying to understand the I2C data buffer concept. According to the Technical Reference Manual v.3.4, chapter 11, page 278, there is a 32 words buffer at REG_I2C_BASE + 0x100. Each byte received or transmitted is stored in the lower 8 bits of a buffer word, the upper 24 bits are unused.

Then: "Users need to set register I2C_NONFIFO_EN".

Q1: For what purpose? Use that buffer? Where is the I2C data stored or read from if I don't set that bit?

Another thing related to the data buffer: In chapter 11.3.4, I2C Cmd Structure, page 280, the "byte_num" field of a command word determines the number of bytes to be transfered in an READ or WRITE command. The bit field has a length of 8 bits and allows values between 1 and 255.

Further down at the bottom of page 281, the doc says "the I2C master can transmit up to (14*255-1) bytes of valid data, and the cmd unit is populated with RSTART + 14 WRITE + 1 STOP". So each WRITE command can transmit 255 bytes of payload data. Which fits to the size of the "byte_num" field.

Q2: How can I transfer 255 (256?) bytes with one command if the data buffer is only 32 * 4 = 128 bytes long? And even stranger, if only the lower 8 bits of a buffer word is used, giving a buffer capacity of 32 bytes if I2C_NONFINO_EN is set?

What am I missing here?

Thanks for your help!
Bass Mati

Not sure because the driver clears I2C_NONFIFO_EN in both master and slave mode, then proceeds to access the fifo using I2C_DATA_APB_REG(). So I guess if it is set you use I2C_DATA_REG() instead. The way you write more bytes is to set a threshold then receive an interrupt and refill the fifo.

Thanks for the response, WiFive!

I found (in the SDK headers) I2C_DATA_APB_REG having an offset of 0x1C to the I2C module base address (0x3FF5.3000 or 0x3FF6.7000) , while RTC_I2C_DATA_REG has an offset of 0x1C to the DR_REG_RTC_I2C_BASE (0x3ff48C00), which seems to be the third I2C module located in the RTC domain.

Unfortunately, both I2C_DATA_APB_REG and RTC_I2C_DATA_REG are not documented in the Technical Reference Manual 3.4...

The use of the threshold interrupts to overwrite stale data with new values is described quite well, although the concept seems a little arkwardly to me. What if the interrupt latency is so large that a WRITE command transfers stale data, or a READ command overwrites unsaved data...?

Any further ideas?

Bass Mati

RTC_I2C_DATA_REG is not related to i2c peripheral.

https://github.com/espressif/esp-idf/bl ... reg.h#L264

APB access is preferred but is used by clearing I2C_NONFIFO_EN not setting it.

You will have to manage interrupt priorities and threshold values to avoid those problems or detect and recover from them.