Clock and power configuration docs

[michprev]

Hi,
please give us more info about RTC, mainly power and clock part. Present version of docs is very unclear about that.

1. Shouldn't it be 80 MHz instead of 120 MHz? https://github.com/espressif/esp-idf/bl ... clk.c#L675
2. What does this do? It is not mentioned in docs. https://github.com/espressif/esp-idf/bl ... clk.c#L699
3. Is not mentioned in docs. Do other bits of this register (except bit 14 and 17) have any function? https://github.com/espressif/esp-idf/bl ... #L701-L703
4. According to what should we configure DBIAS, sleep DBIAS and wake-up DBIAS values?
5. What is RTC_DBOOST and when should it be used?
6. Will this be documented? Are any other XTAL frequencies supported with PLL right configured or 40 MHz, 26 MHz and 24 MHz are the only possible ones? https://github.com/espressif/esp-idf/bl ... #L278-L379
7. Nearly all (maybe all?) clock sources (main XTAL, RTC 8 MHz, RTC 150 kHz, XTAL 32 kHz) can be calibrated using TIMG. How to do that?
8. Ugh? https://github.com/espressif/esp-idf/bl ... .c#L25-L98

[ESP_igrr]

I'll forward the request to colleagues working on documentation; in the meantime, hope this answers some of your questions:

[*] Shouldn't it be 80 MHz instead of 120 MHz? https://github.com/espressif/esp-idf/bl ... clk.c#L675

120 MHz comes from the following logic.
DPORT_CPUPERIOD_SEL=0 is the setting for 80MHz CPU frequency. To get 80MHz CPU frequency and 80MHz APB, source frequency (320MHz) is divided by 4 to get CPU frequency, which is then used directly as APB frequency.
If before reset, CPU frequency was 240MHz, it means that 480MHz PLL was the clock source.
Following the reset, if DPORT_CPUPERIOD_SEL=0, CPU frequency will be 480/4=120 and APB frequency will be the same.

[*] What does this do? It is not mentioned in docs. https://github.com/espressif/esp-idf/bl ... clk.c#L699

It's the divider for 8M RTC clock, which is always set to 0 (no division):
https://github.com/espressif/esp-idf/bl ... reg.h#L932
https://github.com/espressif/esp-idf/bl ... rtc.h#L128

[*] Is not mentioned in docs. Do other bits of this register (except bit 14 and 17) have any function? https://github.com/espressif/esp-idf/bl ... #L701-L703

They probably have some other functions related to WiFi, and perhaps to power detector.

[*] According to what should we configure DBIAS, sleep DBIAS and wake-up DBIAS values?

There are some definitions like DIG_DBIAS_80M_160M, DIG_DBIAS_240M, etc, which provide bias values for different CPU frequencies. As far as i know, these were determined to be safe in the supported temperature range. For sleep, lowest bias value (RTC_CNTL_DBIAS_0V90) is sufficient to provide memory retention.

[*] What is RTC_DBOOST and when should it be used?

This is some unused/experimental feature, it is always disabled by RTC_CNTL_DBOOST_FORCE_PD.

[*] Will this be documented? Are any other XTAL frequencies supported with PLL right configured or 40 MHz, 26 MHz and 24 MHz are the only possible ones? https://github.com/espressif/esp-idf/bl ... #L278-L379

These are the only XTAL frequencies which are supported; In fact, Hardware Design Guide advises to use 40MHz only. W.r.t. register configurations of PLLs, i think it is unlikely that these will be documented.

[*] Nearly all (maybe all?) clock sources (main XTAL, RTC 8 MHz, RTC 150 kHz, XTAL 32 kHz) can be calibrated using TIMG. How to do that?

You can call rtc_clk_cal function (see rtc.h) to calibrate RTC clocks (8MHz, 150kHz/32kHz, 8MHz/256) relative to main XTAL.

[*] Ugh? https://github.com/espressif/esp-idf/bl ... .c#L25-L98

Most of this function deals with clearing various "force power up" bits related to clocks and power. These are normally controlled by state machines, but to reduce the chance that a mistake in one of the state machines will make the whole chip unusable from startup, many of the "force power up" bits are set by default. Disabling them is necessary for things like light sleep and deep sleep.

[michprev]

I'll forward the request to colleagues working on documentation;

Thank you very much. I am aware that more than 90 % of ESP32 users will never ever have to touch any of these settings. On the other hand more complex documentation may attract more business customers (than just hobbyists) and if hardware guys have been working hard to make HW more configurable why not to show all the options in docs, right?

120 MHz comes from the following logic.
DPORT_CPUPERIOD_SEL=0 is the setting for 80MHz CPU frequency. To get 80MHz CPU frequency and 80MHz APB, source frequency (320MHz) is divided by 4 to get CPU frequency, which is then used directly as APB frequency.
If before reset, CPU frequency was 240MHz, it means that 480MHz PLL was the clock source.
Following the reset, if DPORT_CPUPERIOD_SEL=0, CPU frequency will be 480/4=120 and APB frequency will be the same.

I see. Comments say that 120 MHz cannot be used because it would be hard to determine XTAL frequency. That would not be that great problem for me. Is there any hardware limitation?

It's the divider for 8M RTC clock, which is always set to 0 (no division):
https://github.com/espressif/esp-idf/bl ... reg.h#L932
https://github.com/espressif/esp-idf/bl ... rtc.h#L128

Is it that divider?

clk_8m_divider.png (53.6 KiB) Viewed 6983 times

[WiFive]

No that line comes from xtl_clk and is a fixed div/4