Interrupt Priority Levels: Lower Numbers = Higher Prio or vice versa?
Posted: Tue Jun 19, 2018 4:51 pm
Hi folks,
in the ESP32 Technical Reference Manual p.36, chapter 2.3.2 CPU Interrupt, table 9, is a list of CPU interrupts and their priority level numbers, but I can't find a statement about their precedence. Is level 0 the highest (after NMI), or level 5?
And: Can a higher priority interrupt request interrupt a lower priority interrupt service routine?
Thanks in advance
Bass
in the ESP32 Technical Reference Manual p.36, chapter 2.3.2 CPU Interrupt, table 9, is a list of CPU interrupts and their priority level numbers, but I can't find a statement about their precedence. Is level 0 the highest (after NMI), or level 5?
And: Can a higher priority interrupt request interrupt a lower priority interrupt service routine?
Thanks in advance
Bass