ESP32 Forum

Hey there,

I have a question regarding the different clock speeds of the ESP32 which is only confusing me right now.

The technical reference manual (v3.3) states in chapter 3.2 that the speed of the PLL is 320 MHz, which from looking at the esp-idf code is only partly correct since for 240 MHz it has to be 480 MHz from my understanding. Now the reference manual states that the APB clock is derived from the CPU input clock. So for a PLL of 480 MHz according to the manual that would mean 480/4 = 120 MHz. Yet everything states that the APB clock is 80 MHz. Can anybody help me out what I did get wrong? That would be awesome.

Thanks for reading anyways,
have a great day!

There are actually two PLLs, one for 320MHz and one for 480MHz. When CPU frequencies of 80/160MHz are required, 320MHz PLL is used. When 240MHz CPU frequency is required, 480MHz PLL is used.
APB clock in all cases should be set to 80MHz. It is obtained by dividing CPU frequency by a factor of 2 and 3 for 160MHz and 240MHz, respectively, using DPORT_CPUPERIOD_SEL register.

Thanks so much for the very quick reply and clarification!