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GPIO interrupt flags
Posted: Sun Apr 22, 2018 8:43 pm
by rohit269
Hello,
I wanted some clarification regarding the
gpio_install_isr_service(int intr_alloc_flags)
function.
In my system, I have 2 sources of GPIO interrupts on different pins, running in different threads. Therefore I am installing the GPIO ISR service once in the main file. But what argument should I pass to the above function so as to detect both the interrupts seamlessly?
Thanks
Re: GPIO interrupt flags
Posted: Sun Apr 22, 2018 11:51 pm
by mikemoy
Take a look in your esp-idf examples folder under gpio, there is an example how to use it there.
Re: GPIO interrupt flags
Posted: Mon Apr 23, 2018 2:30 am
by rohit269
The example shows how to set up a simple GPIO interrupt which I already understand. I am talking about a case with multiple GPIO interrupts running on different pins, and threads.
How should the
gpio_install_isr_service(int intr_alloc_flags)
be used in that case?
The argument which takes flags are defined in
esp_intr_alloc.h
and are as follows:
#define ESP_INTR_FLAG_LEVEL1 (1<<1) ///< Accept a Level 1 interrupt vector (lowest priority)
#define ESP_INTR_FLAG_LEVEL2 (1<<2) ///< Accept a Level 2 interrupt vector
#define ESP_INTR_FLAG_LEVEL3 (1<<3) ///< Accept a Level 3 interrupt vector
#define ESP_INTR_FLAG_LEVEL4 (1<<4) ///< Accept a Level 4 interrupt vector
#define ESP_INTR_FLAG_LEVEL5 (1<<5) ///< Accept a Level 5 interrupt vector
#define ESP_INTR_FLAG_LEVEL6 (1<<6) ///< Accept a Level 6 interrupt vector
#define ESP_INTR_FLAG_NMI (1<<7) ///< Accept a Level 7 interrupt vector (highest priority)
#define ESP_INTR_FLAG_SHARED (1<<8) ///< Interrupt can be shared between ISRs
#define ESP_INTR_FLAG_EDGE (1<<9) ///< Edge-triggered interrupt
#define ESP_INTR_FLAG_IRAM (1<<10) ///< ISR can be called if cache is disabled
#define ESP_INTR_FLAG_INTRDISABLED (1<<11) ///< Return with this interrupt disabled
#define ESP_INTR_FLAG_LOWMED (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3) ///< Low and medium prio interrupts. These can be handled in C.
#define ESP_INTR_FLAG_HIGH (ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6|ESP_INTR_FLAG_NMI) ///< High level interrupts. Need to be handled in assembly.
#define ESP_INTR_FLAG_LEVELMASK (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \
ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
ESP_INTR_FLAG_NMI) ///< Mask for all level flags
I specifically wanted to know which of these flags would be suitable in my case. The
ESP_INTR_FLAG_SHARED
doesn't seem to be working for me.
Thanks
Re: GPIO interrupt flags
Posted: Mon Apr 23, 2018 4:09 am
by WiFive
Gpio interrupts are already multiplexed into one cpu interrupt so you don't need any flags to make it shared.
Re: GPIO interrupt flags
Posted: Mon Apr 23, 2018 12:17 pm
by rohit269
Just to clarify,
So how can 2 GPIO interrupts(attached to different ISR's) which may occur simultaneously, be detected correctly, if they are ultimately being multiplexed into 1 CPU interrupt? (using the ESP_INTR_FLAG_DEFAULT flag)
Won't they need to keep track of separate flags to correctly activate?
Thanks
Re: GPIO interrupt flags
Posted: Mon Apr 23, 2018 1:14 pm
by WiFive
That is exactly what the gpio isr service does for you
Re: GPIO interrupt flags
Posted: Wed Oct 04, 2023 12:45 pm
by alimoallem
WiFive wrote: ↑Mon Apr 23, 2018 1:14 pm
That is exactly what the gpio isr service does for you
Sorry for keeping alive back a topic after several years but this is my question too. how do GPIO ISR service want to handle this? In my project I need several external GPIO interrupts, but I'm wondering what would happen if two or more pins triggered at the same time? Does GPIO ISR service saves all of them? As the documentation says, all GPIO pins are connected to one source.