ESP32 Forum

I want to port an ESP8266-based (+ host CPU) solution to the ESP32. Currently I have a number (2-4) of high-speed ADCs controlled by a host CPU via SPI using 16-bit data words (hence need 2-4 hardware controlled CSn lines). Samples are then stored to an SD card or transferred via UART to the ESP8266 with a transparent UART-to-WiFi firmware. Now I would like to remove the host CPU and use the ESP32 (actually an ESP-WROOM-32 module) to control the ADCs and stream out raw data directly via a Wi-Fi link using DMA having the Wi-Fi possibly configured as (soft-)AP. The best scenario would be using one core (e.g. CPU0) for continuous ADC sampling and the other core (e.g. CPU1) for continuous data transfer (payload bit rate should be >= 9Mbps!).

My questions:
- Is it possible to configure an SPI (and which one) as a master with 16-bit data word (i.e. assert CS, transfer 16 bit, de-assert CS)?
- Is there any reference on how to configure the SPI registers and use DMA to transfer data to the Wi-Fi stack (TCP/UDP)?

Yes, it's most definitively possible to transfer in 16 bit of information. We're working on SPI documentation and drivers. Documentation probably will be included in the very next documentation release; the driver is scheduled to go into esp-idf 1.0.

Thanks for your answer, this sounds very interesting. Do you think it could be possible to have a preview of the SPI driver? While my question is about the timing I would like to be sure that SPI and GPIO are fast enough to control 4 devices (even using 4x GPIOs as chip select).