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.check_dport_access_end:
    l32i    a3, a2, 0
    beqz    a3, .check_dport_access_end

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REG_READ(SPI_DATE_REG(3));

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/* stall other cpu that this cpu is pending to access dport register start */
void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
{
#ifndef CONFIG_FREERTOS_UNICORE
    if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
        || dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
        return;
    }

    BaseType_t intLvl = portENTER_CRITICAL_NESTED();

    int cpu_id = xPortGetCoreID();

#ifdef DPORT_ACCESS_BENCHMARK
    ccount_start[cpu_id] = XTHAL_GET_CCOUNT();
#endif

    if (dport_access_ref[cpu_id] == 0) {
        portENTER_CRITICAL_ISR(&g_dport_mux);

        oldInterruptLevel[cpu_id]=intLvl;

        dport_access_start[cpu_id] = 0;
        dport_access_end[cpu_id] = 0;

        if (cpu_id == 0) {
            _DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_3_REG, DPORT_CPU_INTR_FROM_CPU_3); //interrupt on cpu1
        } else {
            _DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_2_REG, DPORT_CPU_INTR_FROM_CPU_2); //interrupt on cpu0
        }

        while (!dport_access_start[cpu_id]) {};

        // !!! APP CPU was at the following instruction during the WDT-caused reset
        REG_READ(SPI_DATE_REG(3));  //just read a APB register sure that the APB-bus is idle
    }

    dport_access_ref[cpu_id]++;

    if (dport_access_ref[cpu_id] > 1) {
        /* Interrupts are already disabled by the parent, we're nested here. */
        portEXIT_CRITICAL_NESTED(intLvl);
    }
#endif /* CONFIG_FREERTOS_UNICORE */
}