SPI configurable segmented transfer
Posted: Tue Sep 24, 2024 7:17 am
We implemented an SPI driver that allows to write/read from/to circular buffers in continuous mode, managed by DMA.
With ESP32 : There is a register bit DMA_CONTINUE that can be set. With circular linked lists it is easy to get it running. Absolutely no cache miss or delays since all is managed by hardware.
With ESP32-C3 and other modules with GDMA : the register bit DMA_CONTINUE doesn't exist anymore. So we have to use configurable segmented transfer to achieve a continuous mode. The problem is there is a delay of 5 clock period that seems unavoidable between each segment. That leads to a loss of sampling frequency that we would like to avoid. Is there any other way ? Does the DMA_CONTINUE register bit still exists but not documented ?
With ESP32 : There is a register bit DMA_CONTINUE that can be set. With circular linked lists it is easy to get it running. Absolutely no cache miss or delays since all is managed by hardware.
With ESP32-C3 and other modules with GDMA : the register bit DMA_CONTINUE doesn't exist anymore. So we have to use configurable segmented transfer to achieve a continuous mode. The problem is there is a delay of 5 clock period that seems unavoidable between each segment. That leads to a loss of sampling frequency that we would like to avoid. Is there any other way ? Does the DMA_CONTINUE register bit still exists but not documented ?